(For HW 7, Design an 8-bit add/subtract in Verilog AND VHDL using any of the cod

Question

(For HW 7, Design an 8-bit add/subtract in Verilog AND VHDL using any of the coding styles and language features covered so far in modules 8 and 9. When AS_Sel = 0 it

performs an addition, else when AS_Sel = 1 it performs a subtraction. OpA and OpB are assumed to be signed, 2’s-Complement numbers. Hint: Bit-wise XOR AS_Sel with OpB before adding it to OpA).

For the 8-bit add/subtract circuit created in hw7, write a Verilog AND a VHDL testbench. Test ONLY the following input vectors AS Sel OpB 0x00 0x00 0x55 0x55 0xAA Result Cout Vout 0x00 0x00 0x55 0x55 0xAA 0xAA 0xFF 0xFF 0 0 0xFF 0xFF Fil in the table with the expected good output values. Show the complete testbench code OpA/7 0 Add/Subtract Re Cout AS Sel

Explanation / Answer

// 8 bit Full Adder/Subtractor design   
module add_sub (

input [7:0] OpA,

// input A

input [7:0] OpB, // input B

input AS_Sel, // Sel = 0 addition , Sel = 1 subtract

output [7:0] Result,

// Sum of A + B

output Cout,

// Carry out of addition

output Vout

// Overflow flag
);

wire c0, c1, c2, c3, c4, c5, c6, c7;
wire b0, b1, b2, b3, b4, b5, b6, b7;

xor (b0, OpB[0], AS_Sel);
xor (b1, OpB[1], AS_Sel);
xor (b2, OpB[2], AS_Sel);
xor (b3, OpB[3], AS_Sel);
xor (b4, OpB[4], AS_Sel);
xor (b5, OpB[5], AS_Sel);
xor (b6, OpB[6], AS_Sel);
xor (b7, OpB[7], AS_Sel);

xor (Cout, c7, AS_Sel);

// Cout = c7 for addition ; Cout = ~c7 for subtraction
xor (Vout, c7, c6);

// Overflow Flag

full_adder FA0 (Result[0], c0, OpA[0], OpB[0], AS_Sel);
full_adder FA1 (Result[1], c1, OpA[1], OpB[1], AS_Sel);
full_adder FA2 (Result[2], c2, OpA[2], OpB[2], AS_Sel);
full_adder FA3 (Result[3], c3, OpA[3], OpB[3], AS_Sel);
full_adder FA4 (Result[4], c4, OpA[4], OpB[4], AS_Sel);
full_adder FA5 (Result[5], c5, OpA[5], OpB[5], AS_Sel);
full_adder FA6 (Result[6], c6, OpA[6], OpB[6], AS_Sel);
full_adder FA7 (Result[7], c7, OpA[7], OpB[7], AS_Sel);

endmodule


// 1 bit Full adder design
module full_adder (

output Sum,

output Cout,

input A,

input B,

input Cin);

wire w1, w2, w3;


and (w1, A, B);
and (w2, A, Cin);
and (w3, A, Cin);
or (Cout, w1, w2, w3);
xor (Sum, A, B, Cin);

endmodule

// Test bench for the module
module add_sub_tb ();

reg [7:0] OpA;
reg [7:0] OpB;
reg AS_Sel;
wire [7:0] Result;
wire Cout;
wire Vout;


add_sub m1 (.OpA(OpA), .OpB(OpB), .AS_Sel(AS_Sel), .Result(Result), .Cout(Cout), .Vout(Vout));

initial
  begin

$monitor ("OpA = %H, OpB = %H, AS_Sel = %b, Result = %H, Cout = %b, Vout = %b", OpA, OpB, AS_Sel, Result, Cout, Vout);

OpA = 8'h00; OpB = 8'h00; AS_Sel = 0; #10;

// Apply the inputs

OpA = 8'h00; OpB = 8'h00; AS_Sel = 1; #10;

OpA = 8'h55; OpB = 8'h55; AS_Sel = 0; #10;

OpA = 8'h55; OpB = 8'h55; AS_Sel = 1; #10;

OpA = 8'hAA; OpB = 8'hAA; AS_Sel = 0; #10;

OpA = 8'hAA; OpB = 8'hAA; AS_Sel = 1; #10;

OpA = 8'hFF; OpB = 8'hFF; AS_Sel = 0; #10;

OpA = 8'hFF; OpB = 8'hFF; AS_Sel = 1; #10;
  end

endmodule

/*
Result of the code is here
OpA = 00, OpB = 00, AS_Sel = 0, Result = 00, Cout = 0, Vout = 0
OpA = 00, OpB = 00, AS_Sel = 1, Result = ff, Cout = 1, Vout = 0
OpA = 55, OpB = 55, AS_Sel = 0, Result = 00, Cout = 0, Vout = 1
OpA = 55, OpB = 55, AS_Sel = 1, Result = ff, Cout = 1, Vout = 1
OpA = aa, OpB = aa, AS_Sel = 0, Result = 00, Cout = 1, Vout = 1
OpA = aa, OpB = aa, AS_Sel = 1, Result = ff, Cout = 0, Vout = 1
OpA = ff, OpB = ff, AS_Sel = 0, Result = 00, Cout = 1, Vout = 0
OpA = ff, OpB = ff, AS_Sel = 1, Result = ff, Cout = 0, Vout = 0

*/

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