VHDL Problem: Question: Create a Quartus project which contains a file: - ALU.vh

Question

VHDL Problem:

Question:

Create a Quartus project which contains a file:
- ALU.vhd: The VHDL description of the 32-bit ALU described above. Simulate your design and make sure it generates the correct output

ENA INVA ENB Zero Status 2 F1Fo ALU Negative Status Result A,B The 32-bit inputs to be manipulated FiFo The 2 bits that control the operation to be performed on A and B (see table below) ENA A bit that Enables ALU A input (see table below). INVA A bit that Inverts ALU A input (see table below). ENB A bit that Enables ALA B input (see table below) Zero Set if Result = 0, reset otherwise. Neg The sign bit (MSB) of the result Result The 32-bit outcome of the operation. Signal Name Width Description Value Meaning 0 AND 1 NOT B F,Fo Function 2 Basic ALU function 2 OR 3 ADD 0 Force A input to zero ENA Enable A 1 Enable ALU A input 1 Use A input value 0 Do not invert A input value INVA Invert A 1 Invert ALU A input 1 Invert A input value 0 Force B input to zero ENB Enable B 1 Enable ALU B input 1 Use B input value

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
port (
A,B:in std_logic_vector (31 downto 0);
F:in std_logic_vector (1 downto 0);
ENA: in std_logic;
INVA: in std_logic;
ENB: in std_logic;
CLK: in std_logic;
RESULT: out std_logic_vector (31 downto 0);
ZERO: out std_logic;
NEG: out std_logic
);
end ALU;

architecture beh of ALU is
signal A_inv : std_logic_vector(31 downto 0);
signal A_e,B_e : std_logic_vector (31 downto 0);
signal RES: std_logic_vector (31 downto 0);
begin
  
process (A,B,ENA,INVA,ENB,CLK)

begin
  
if (CLK'event and CLK='1') then
if (ENA='1') then
A_e<=A;
elsif (INVA='1') then
A_e<=not A_e;
end if;
  
if (ENB='1') then
B_e<=B;
else
B_e<=(others=>'0');
end if;

  
case F is
when "00" => RES<= A_e and B_e;
when "01" => RES <= not B_e;
when "10" => RES <= A_e or B_e;
when others => RES <= A_e + B_e;
end case;
  
if (RES="00000000000000000000000000000000") then
ZERO<='1';
else
ZERO<='0';
end if;
  
if (RES(31)='1') then
NEG<='1';
else
NEG<='0';
end if;

end if;
  
RESULT<=RES;
  
end process;
  
end beh;

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