Suppose registers R0 and R1 already hold single 64-bit quantity witht he most si

Question

Suppose registers R0 and R1 already hold single 64-bit quantity witht he most significant 32 bits in R1

10. Suppose registers RO and R1 already hold single 64-bit quantity with the most n RI and the least significant shoquired to significant 32 bits in RI and the least significant 32 bits in RO. Give a minimum- length sequence of ARM Cortex-M3 instructions that would be required to implement: (a) A 64-bit logical right shift by 1-bit position (b) A 64-bit arithmetic right shift by 1-bit position (c) A 64-bit right rotate (not including the carry flag) by 1-bit position

Explanation / Answer

a)A LOGICAL left right:

b)

A LOGICAL shift right:

c)Right Rotate

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