Write Verilog module(s) for a two-bit arithmetic logic unit (ALU). The ALU recei
ID: 2085869 • Letter: W
Question
Write Verilog module(s) for a two-bit arithmetic logic unit (ALU). The ALU receives two inputs A and B, each two bits (A=a1a0 and B=b1b0) and performs logical operations (AND, OR, XOR, NOT, shift left logical, shift right logical) and unsigned addition and multiplication. The ALU multiplexes only one result from one of the logical operations or arithmetic operations to the output. Write a testbench for your design. Verify each operation of your ALU using the following test vectors. a = 2’b00; b = 2’b00;
a = 2’b11; b = 2’b11;
a = 2’b01; b = 2’b10;
Write Verilog module(s) for a two-bit arithmetic logic unit (ALU). The ALU receives two inputs A and B, each two bits (A=a1a0 and B=b1b0) and performs logical operations (AND, OR, XOR, NOT, shift left logical, shift right logical) and unsigned addition and multiplication. The ALU multiplexes only one result from one of the logical operations or arithmetic operations to the output. Write a testbench for your design. Verify each operation of your ALU using the following test vectors. a = 2’b00; b = 2’b00;
a = 2’b11; b = 2’b11;
a = 2’b01; b = 2’b10;
Explanation / Answer
module alu_new (A,B,rst,clk,OUT,opcode);
input [1:0] A,B;
input clk,rst;
input [2:0] opcode;
output reg [3:0] OUT;
always @(posedge(clk) or negedge(rst))
begin
if(!rst)
OUT<=4'b0;
else
case(opcode)
3'b000: {OUT[3:2],OUT[1:0]} <= {2'b00,A & B}; //AND
3'b001: {OUT[3:2],OUT[1:0]} <= {2'b00,A | B}; //OR
3'b010: {OUT[3:2],OUT[1:0]} <= {2'b00,A ^ B}; //XOR
3'b011: {OUT[3:2],OUT[1:0]} <={2'b00, ~ A}; //NOT
3'b100: {OUT[3:2],OUT[1:0]} <= {2'b00,A << 1}; //SHIFT LEFT
3'b101: {OUT[3:2],OUT[1:0]} <= {2'b00,A >> 1}; //SHIFT RIGHT
3'b110: {OUT[3],OUT[2:0]} <= {1'b0,A+B}; // ADD
3'b111: OUT <= A * B; //MULTIPLY
endcase
end
endmodule
module test;
reg [1:0] A,B;
reg clk,rst;
reg [2:0] opcode;
wire [3:0] OUT;
integer i;
alu_new a1 (A,B,rst,clk,OUT,opcode);
always #5 clk=!clk;
initial
begin
clk=0;
@(negedge clk)
rst=0;
@(negedge clk)
rst=1;
A=2'b00;
A=2'b00;
for (i=0;i<8;i=i+1)
begin
@(negedge clk)
opcode=i;
end
A=2'b11;
A=2'b11;
for (i=0;i<8;i=i+1)
begin
@(negedge clk)
opcode=i;
end
A=2'b01;
A=2'b10;
for (i=0;i<8;i=i+1)
begin
@(negedge clk)
opcode=i;
end
$finish;
end
initial
begin
$monitor("%t A=%b B=%b rst=%b opcode=%b OUT=%b",$time,A,B,rst,opcode,OUT);
end
endmodule
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