0 ns O ns 960 0 ps d2 B 0 8 0 B 0 do Figure 8.2 Majority Vote Simulation Procedu
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0 ns O ns 960 0 ps d2 B 0 8 0 B 0 do Figure 8.2 Majority Vote Simulation Procedure Encoding a Circuit with a Concurrent Signal Assignment Statement Refer to the half-adder circuit shown in Figure 8.3. XOR Input AND2 Output carry out Figure 8.3 Half-Adder Circuit Design Entry Create a new folder called drive:lqdesignslabsMab0Sthalf_addl. Use the Quartus I Text Editor to enter the VHDL file for the half-adder circuit, using a concurrent signal assignment statement, as described in the Experimental Notes for this lab exercise. Save the file as drive:qdesignslabsUabosthalf addhalf add.vhd and use the file to create a project in Quartus II. (Make sure that the box labeled Create new project based on this file is checked.) 67Explanation / Answer
The half adder is a logical circuit that adds two one-digit numbers.It has one sum bit which represents the sum and carry bit which represents the carry.
Simulation Criteria
• Group the inputs together as a single unit: d[1..0].
• Apply an increasing binary count, from 00 to 11, to the d[1..0]group.
• The sum output,y,should go HIGH for input values 01,10.
Simulation:
—table1.vhd
—Truth table, encoded using a selected signal assignment statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY table1 IS
PORT(
d: IN STD_LOGIC_VECTOR (1 downto 0);
y: OUT STD_LOGIC);
END table1;
ARCHITECTURE a OF table1 IS
BEGIN
WITH d SELECT
y <= ‘1’ WHEN “01”,
‘1’ WHEN “10”,
‘0’ WHEN others;
END a
The Entity for the half adder :
library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port (a : in std_logic;
b : in std_logic;
sum : out std_logic;
cout : out std_logic);
end half_adder;
The Behavior Model for the half adder :
architecture basic_beh of half_adder is
begin
process (a,b)
begin
if (a = '1' and b = '1') then
sum <= '0' ;
cout <= '1';
elsif (a = '1' and b = '0') then
sum <= '1' ;
cout <= '0';
elsif (a = '0' and b = '1' )then
sum <= '1' ;
cout <= '0';
elsif (a = '0' and b = '0') then
sum <= '0' ;
cout <= '0';
else
sum <= '0' ;
cout <= '0';
end if;
end process;
end basic_beh;
The Structural Model for the half adder :
architecture basic_struct of half_adder is
begin
and1: entity work.and2(basic_and)
port map (a,b,cout);
xor1: entity work.XOR2(basic_XOR)
port map (a,b,sum);
end basic_struct;
The And gate :
library IEEE;
use IEEE.std_logic_1164.all;
entity and2 is
port (x : in std_logic;
y : in std_logic;
z : out std_logic );
end and2;
architecture basic_and of and2 is
begin
z <= x and y;
end basic_and;
The XOR gate :
library IEEE;
use IEEE.std_logic_1164.all;
entity XOR2 is
port (x : in std_logic;
y : in std_logic;
z : out std_logic );
end XOR2;
architecture basic_XOR of XOR2 is
begin
z <= x and y;
end basic_XOR;
The Test bench
library ieee;
use ieee.std_logic_1164.all;
entity half_adder_tb is
end half_adder_tb;
architecture TB_ARCHITECTURE of half_adder_tb is
-- Stimulus signals - signals mapped to the input
--and inout ports of tested entity
signal a : std_logic;
signal b : std_logic;
-- Observed signals - signals mapped to the output
--ports of tested entity
signal sum : std_logic;
signal cout : std_logic;
begin
-- Design Under Test port map
DUT : entity work.half_adder(basic_struct)
port map (
a => a,
b => b,
sum => sum,
cout => cout
);
-- your stimulus here ...
stimulus: process is
begin
a <='0',
'1' AFTER 10 ns,
'0' AFTER 30 ns,
'1' AFTER 40 ns;
b <='0',
'0' AFTER 10 ns,
'1' AFTER 30 ns,
'1' AFTER 40 ns;
wait;
end process stimulus;
end TB_ARCHITECTURE;
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