Below is a working 1-bit ALU. I am now trying to make an 8-bit ALU with this. mo

Question

Below is a working 1-bit ALU. I am now trying to make an 8-bit ALU with this.

module ALUSlice(A,B,CI,M,S,F,CO);
input A,B,CI,M,S;
output F,CO;
wire [3:0] TF;
wire [3:0] TC;

FullAdder F1(TF[3],TC[3],A,B,CI);
assign TF[0] = A & B;
assign TF[1] = A | B;
assign TF[2] = ~A;

assign TC[2:0] = 0;
Dual4to1Mux Mux1(F,CO,{M,S},TF,TC);
endmodule

This i what I have so far of my 8-bit ALU but it doesn't pass the test bench

module ALU8Bit(S1,S0, A, B, CarryIn, CarryOut, F);
input [7:0] A,B;
input S1,S0,CarryIn;
output [7:0] F;
output CarryOut;

wire [7:0] C;

ALUSlice A0(F[0],C[0],A[0],B[0],CarryIn,S0,S1);
ALUSlice A1(F[1],C[1],A[1],B[1],C[0],S0,S1);
ALUSlice A2(F[2],C[2],A[2],B[2],C[1],S0,S1);
ALUSlice A3(F[3],C[3],A[3],B[3],C[2],S0,S1);
ALUSlice A4(F[4],C[4],A[4],B[4],C[3],S0,S1);
ALUSlice A5(F[5],C[5],A[5],B[5],C[4],S0,S1);
ALUSlice A6(F[6],C[6],A[6],B[6],C[5],S0,S1);
ALUSlice A7(F[7],CarryOut,A[7],B[7],C[6],S0,S1);

endmodule

Explanation / Answer

From the above code, if we consider, for module ALUSlice(A,B,CI,M,S,F,CO) :

A,B - input , CI - carry input

M,S - select lines for the multiplexer

F , CO - output (sum etc) and output carry

then,

the declaration of modules being done in the ALU8Bit(S1,S0, A, B, CarryIn, CarryOut, F); is wrong.

The order of the parameters is wrong. Instead of (for example): ALUSlice A0(F[0],C[0],A[0],B[0],CarryIn,S0,S1);

it should instead be : ALUSlice A0(A[0],B[0],CarryIn,S0,S1,F[0],C[0]);

Hence, the whole module can be changed as follows :

module ALU8Bit(S1,S0, A, B, CarryIn, CarryOut, F);
input [7:0] A,B;
input S1,S0,CarryIn;
output [7:0] F;
output CarryOut;

wire [7:0] C;

ALUSlice A0(A[0],B[0],CarryIn,S0,S1,F[0],C[0]);
ALUSlice A1(A[1],B[1],C[0],S0,S1,F[1],C[1]);
ALUSlice A2(A[2],B[2],C[1],S0,S1,F[2],C[2]);
ALUSlice A3(A[3],B[3],C[2],S0,S1,F[3],C[3]);
ALUSlice A4(A[4],B[4],C[3],S0,S1,F[4],C[4]);
ALUSlice A5(A[5],B[5],C[4],S0,S1,F[5],C[5]);
ALUSlice A6(A[6],B[6],C[5],S0,S1,F[6],C[6]);
ALUSlice A7(A[7],B[7],C[6],S0,S1,F[7],CarryOut);

endmodule

The order of the parameters matter while invoking any external module from the present code.

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