SHORT QUESTION / MULTIPLE OPTION What would be the output frequency of a three s

Question

SHORT QUESTION / MULTIPLE OPTION

What would be the output frequency of a three stage [three flip flop] frequency division circuit with an input clock frequency of 80 kHz?

Question 1 options:

100 kHz

20 kHz

15 kHz

10 kHz

5 kHz

1 kHz

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Question 2 (1 point)

Determine the output frequency for a frequency division circuit that contains twelve flip-flops with an input clock frequency of 20.48 MHz

Question 2 options:

1.707 MHz

30.24 kHz

15 kHz

10.24 kHz

5 kHz

50 Hz

10.24 Hz

5 Hz

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Question 3 (1 point)

The difference between a three-stage up counter and a down counter is the fact that:

Question 3 options:

An up counter's count decreases by one with each input clock pulse, whereas a down counter's count increases by one with each input clock pulse.

An up counter's count increases by one with each input clock pulse, whereas a down counter's count decreases by one with each input clock pulse.

An up counter currently in state 000 would change to 001 on the next state transition, whereas a down counter currently in state 000 would change to 111 on the next state transition.

Both B and C

Both A and C

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Question 4 (1 point)

A production plant has a requirement for a counter that will count 4,000 items before recycling and starting over. How many D flip-flop stages would be required in this counter?

Question 4 options:

9

10

11

12

13

14

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Question 5 (2 points)

If one desires to count to M, what is the minimum number of bits (K) required in the
resulting counter? [ denotes the ceiling function ]

To help answer this question, you may wish to review Powers, Logs and Ceiling Function.

Question 5 options:

K=log2(M)

K=log2(M)

K=log2(M+1)

K=log2(M+1)

K=log2(M1)

K=log2(M-1)

K=2M1

K=2M

A)

100 kHz

B)

20 kHz

C)

15 kHz

D)

10 kHz

E)

5 kHz

F)

1 kHz

Explanation / Answer

Question 1: D (10 KHZ)

The output frequency = input frequency / (2 ^ N)

N = number of flip-flops

So here N = 3

output frequency = input frequency / (2 ^ 3)

output frequency = 80 KHZ / 8 =10KHZ

Question 2 : E (5 KHZ)

simillary above Here N = 12

output frequency = input frequency / (2 ^ 12)

output frequency = 20.48 MHZ / 4096  

output frequency = 20480000/ 4096 = 5000 = 5KHZ

Question 3 :    Both B and C

An up counter's count increases by one with each input clock pulse, whereas a down counter's count decreases by one with each input clock pulse. It is increments 0 ->1 -> 2 ->3->4->5->6->7->0

An up counter currently in state 000 would change to 001 on the next state transition, whereas a down counter currently in state 000 would change to 111 on the next state transition. It decrements

0->7->6->5->4->3->2->1 ->0

Question 4 : 12

because 2^12 >= 4000 = 4096>= 4000

Question 5 : K=log2(M+1)

if Count =8 the maximum number of bits log2(9) = 3

so 000 -> 111

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