Design and implementation of 8 bit serial/ parallel input serial output shift re

Question

Design and implementation of 8 bit serial/ parallel input serial output shift register using behavioral style of modelling.

I'm using 74LS166 8-BIT SHIFT REGISTERS IC.

This code is serial input serial output but not sure. plz check it?

Shall you provide or type the code of parallel input serial output??

library ieee;

use ieee.std_logic_1164.all;

entity SReg is

generic (

     n : integer := 4

    );

port(

    clk:              in std_logic;

    reset:            in std_logic;

    enable:           in std_logic;    --enables shifting

    parallel_in:      in std_logic_vector(n-1 downto 0);

    s_in:             in std_logic;    --serial input

    s_out:            out std_logic   --serial output

    );

end SReg;

architecture behavioral of SReg is

signal temp_reg: std_logic_vector(n-1 downto 0) := (Others => '0');

begin

process (clk,reset)

begin

    if (reset = '1') then

      temp_reg <= parallel_in;  

    elsif (clk'event and clk='1') then

      if (enable ='1') then

        --shifting n number of bits

        for i in 0 to n-1 loop

          s_out <= temp_reg(0);

          temp_reg <= s_in & temp_reg(n-1 downto 1);

        end loop;

      end if;

    end if;

end process;

end behavioral;

Explanation / Answer

CODE FOR SERIAL INPUT SERIAL OUTPUT

there is problem with the for loop in your code. In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code.The entire loop is executing in a single clock cycle, and the value of s_out is only going to change once - to the value it was when the loop ended, which in this case is s_in shifted by 4.

What you really want is a loop where each iteration occurs on a new clock edge. This allows for s_in to be shifted out of s_out ever clock cycle.

Performing a loop where each iteration occurs on a clock edge does not require a for loop command, instead it takes advantage of the sensitivity list of the process. Here's how:

A process is triggered every time one of the signals on the sensitivity list ("clk, reset" in this case) changes. This means that the process is already looping every clock cycle (if a clock is in the sensitivity list). You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle.

First you need a counter:

shift_counter keeps track of how many iterations (or shifts) have occurred so far. you'll compare shift_counter to n-1 to see if you're done yet.

Next it might be a good idea to think of the states your process will be in. Perhaps a wait state for when the process is not shifting, and a shifting state for when it is.

The state signal definition:

In the process proper:

Ok, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. This means that maybe something like this is a good idea:

This is useful to do because then you know exactly what your signal values are when enable goes high. Also, at the end of the shift, you can change states back to "waiting" in order to get ready for enable again.

So what is going to trigger a state change from waiting to shifting ? That's easy:

Ok, so next state. shifting.

First, we want to increment the shift counter, and perform the actual shift:

And then also detect when the shifting is done, in order to leave the shift state and go back to waiting:

CODE FOR PARALLEL INPUT SERIAL OUTPUT

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC
);
end parallel_in_serial_out;

architecture piso_arc of parallel_in_serial_out is
begin

piso : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
elsif (rising_edge (clk)) then
dout <= temp(7);
temp := temp(6 downto 0) & '0';
end if;
end process piso;

end piso_arc;

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