In this lab you will design and build a sequence detector and build a multiplexe

Question

In this lab you will design and build a sequence detector and build a multiplexer circuit in VHDL. In your lab group, design a Moore machine to detect the sequence below. Your circuit must detect overlapping sequences. Use a switch to change the inputs (you will need a slow clock, in the 200 mHz range). LEDs can be used to indicate the slate (Q), and hence the correct progression through the state machine. In order to complete the lab, you must do the following. a. Derive the state diagram. b. Derive the state table and flip-Hop excitation equations. If you have unused states, you have the option of using don't cares or forcing your state machine to return to a given state(s). If don't cares are used, be sure to update the state diagram to ensure a self-correcting state machine. Verily that your circuit is self-correcting. c. Draw the sequential circuit using flip-flops and decoders or multiplexers. d. Simulate the sequence detector using the logic analyzer on MultiSim and build the circuit on a breadboard using logic gates and/or MSIs. Use an LED to indicate the state and verify functionality of the circuit. e. Demonstrate it to your instructor in the lab. Design Problem 10A (in your textbook) describes the design of a 4-to-1 MUX using 2-to-1 MUXES. Design and simulate this circuit in MultiSim. Then, design your own 2-to-1 MUX in VHDL using www.edaplayground.com and use this MUX to implement a 4-to-1 MUX. Note, your input and outputs should be of the type std_logic (not bit, as written in the textbook)

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity depun_mux_out is
Port ( in1 : in std_logic; -- mux input1
in2 : in std_logic; -- mux input2
in3 : in std_logic; -- mux input3
in4 : in std_logic; -- mux input4
sel : in std_logic_vector(1 downto 0); -- selection line
dataout : out std_logic); -- output data
end depun_mux_out;

architecture Behavioral of depun_mux_out is

begin
-- This process for mux logic
process (sel, in1, in2, in3, in4)
begin
case SEL is
when "00" => dataout <= in1;
when "01" => dataout <= in2;
when "10" => dataout <= in3;
when "11" => dataout <= in4;
when others => dataout <= '0';
end case;
end process;

end Behavioral;

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