For the questions on this page, consider an SRAM that uses coincident selection

ID: 2083303 • Letter: F

Question

For the questions on this page, consider an SRAM that uses coincident selection as shown in the below figure. Remember that in our terminology, a column is a group of bitslices that are selected simultaneously.

The SRAM has 10 address lines. The data width is 16 bits. Assume that SRAM cell array is to be constructed so that the row and column decoders are the same size.

a. How many outputs does the row decoder have?

b. How many columns does the SRAM cell array have?

c. How many bitslices does the SRAM cell array have?

ADR- 24 R-1 m m DIN- C-1 DOUT column decoder CS R/W .gao!IS1iq ZaDIS1ig Tao!IS1iq 11 0a0IS1iq 111 0 0 01234 epooap MOJ k NS DC

Explanation / Answer

a.the row decoder has R-1 outputs.

c.the bitslices have B-1

b.the coulumns have C-1

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For the questions on this page, consider an SRAM that uses coincident selection

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