Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

A shifter is a block that takes an n-bit word and changes the significance of ea

ID: 2083242 • Letter: A

Question

A shifter is a block that takes an n-bit word and changes the significance of each bit position of the word (a) Draw the design of a block that optionally shifts an 8-bit 2's complement word by 2 bit positions to the left (toward the MsB) when a shift_ left2 = 1'b1 and does not shift when shift_ left 2 = 1'b0. How does this change the value of the word? Build this with 2:1 multiplexers (b) If the design in (a) is instead optionally shifting to the right (toward the LSB) with a shift_ right = 1'b1, what change would be needed to the design? How does this change the value of the word? You can choose to do either logical or arithmetic shift but you need to specify this clearly (c) Draw the design of a variable shifter that can arbitrarily shift in either direction based on a 1-bit input, dir, for direction (dir =1'b1 for left shift and dir =1'b0 for right shift) and 3-bit binary input, shift[2:0], indicating the amount of shift (up to 7). Try to use the least number of 3:1 multiplexers. Each 3-input multiplexers accepts 3-inputs {top, mid, bot} and 3 select signals (1-hot) {selt, selm, selb} to select each of those inputs. (d) What is a barrel-shifter? How would you change the design in (c) to implement this Answer the question for all parts in the space below.

Explanation / Answer

A barrel shifter is a digital circuit that can shift a data word by a specified number of bits without the use of any sequential logic, only pure combinatorial logic. One way to implement it is as a sequence of multiplexers where the output of one multiplexer is connected to the input of the next multiplexer in a way that depends on the shift distance. A barrel shifter is often used to shift and rotate n-bits in modern microprocessors, typically within a single clock cycle.

For example, take a four-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA; in this case, no bits are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including being a useful component in microprocessors (alongside the ALU).

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity barrel_shifter is port ( d_in : in std_logic_vector(7 downto 0); -- input vector d_out : out std_logic_vector(7 downto 0); -- shifted output shift_lt_rt : in std_logic; -- 0=>left_operation 1=>right_operation shift_by : in std_logic_vector(2 downto 0); -- shift amount clk : in std_logic; -- clock signal rst_a : in std_logic; -- reset signal p_load : in std_logic); -- parallel load end barrel_shifter; architecture beh of barrel_shifter is begin -- beh p1: process (clk,rst_a,shift_by,shift_lt_rt) variable x,y : std_logic_vector(7 downto 0); variable ctrl0,ctrl1,ctrl2 : std_logic_vector(1 downto 0); begin -- process p1 ctrl0:=shift_by(0) & shift_lt_rt; ctrl1:=shift_by(1) & shift_lt_rt; ctrl2:=shift_by(2) & shift_lt_rt; if(rst_a = '1') then d_out<="00000000"; elsif(clk'event and clk = '1') then if (p_load='0')then assert(false) report "Parallel load low" severity warning; elsif(shift_lt_rt='1')then assert(false) report "right shift" severity warning; elsif(shift_lt_rt='0')then assert(false) report "left shift" severity warning; end if; if p_load='1' then case ctrl0 is when "00"|"01" =>x:=d_in ; when "10" =>x:=d_in(6 downto 0) & d_in(7); --shift left by 1 bit when "11" =>x:=d_in(0) & d_in(7 downto 1); --shift right by 1 bit when others => null; end case; case ctrl1 is when "00"|"01" =>y:=x; when "10" =>y:=x(5 downto 0) & x(7 downto 6); --shift left by 2 bits when "11" =>y:=x(1 downto 0) & x(7 downto 2); --shift right by 2 bits when others => null; end case; case ctrl2 is when "00"|"01" =>d_out<=y ; when "10"|"11" =>d_out<= y(3 downto 0) & y(7 downto 4); --shift right/left by 4 bits when others => null; end case; end if; end if; end process p1; end beh;

Hire Me For All Your Tutoring Needs
Integrity-first tutoring: clear explanations, guidance, and feedback.
Drop an Email at
drjack9650@gmail.com
Chat Now And Get Quote