A. Write the code in VHDL and Provide the XDC file. B. Provide a Testbanch and S

Question

A. Write the code in VHDL and Provide the XDC file.

B. Provide a Testbanch and Simulation

Clock Output (Coffee/Tea) Reset Input Coffee (Coffee/Tea) Vending One Dollar Machine One Dollar Two Dollars Two Dollars Five Dollars A typical Vending Machine is shown in the above figure As observed, this machine has six in 1. Clock 2. Reset 3. Input (1 Coffee & 0 Tea 4. One Dollar ($1) 5. Two Dollars ($2) 6. Five Dollars ($5) And has three outputs: l. Output (Coffee or Tea) 2. One Dollars (S1) 3. Two Dollars ($2) Cost of Tea is $2 and cost of Coffee is $3. You have an output as high when either of the two is delivered The implementation ofthis program on an FPGA requires 3 steps to be completed: Part 1: Your Vending Machine program Part 2: Clock divider (for using the internal clock at a reduced frequency) Part 3: Top module for implementing the two (Hint: Structural coding)

Explanation / Answer

XUP has developed and laboratory exercises for use with the XUP supported boards. The laboratory material is targeted for use in a introductory Digital Design course where professors want to include FPGA technology in the course to validate the learned principles through creating designs using Vivado.

The is delevloped to get the users (students) introduced to the digital design flow in Xilinx All Programmable devices using Vivado design software suite. The laboratory exercises include fundamental HDL modeling principles and problem statements. Professors can assign the desired exercises provided in each laboratory document. They also can make a separate request to access the source codes for the laboratory exercises. Number of exercises provide enough material for a semester-long course, considering couple of weeks spent in mid-term and final exams during a semester.

Complete source deck for each of the exercises is available to the professors. Professors who are interested in obtaining the complete source deck, please send email to XUP stating the language (Verilog/VHDL) in the message body and providing complete title, email address, and the university address.

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