Hello. I only need help with problem 8.39. I have proveded the solution for prob

Question

Hello. I only need help with problem 8.39.

I have proveded the solution for problem 8.38. Problem 8.39 needs VHDL code for the FSM designed in problem 8.38.

Thank you!

8.38 The arbiter FSM defined in section 8.8 (Figure 8.72) may cause device 3 to never get serviced if devices 1 and 2 continuously keep raising requests, so that in the Idle state it always happens that either device 1 or device 2 has an outstanding request. Modify the The solution for problem 8.38 is below: To ensure that the device 3 will get serviced the FSM in Figure 8.72 can be modified as follows: Reset 00 Idle 000 1xx gntl/g1 1 x00 01x 01x 001 gnt2/g2 x01 001 x1x gnt3/g3-1 CHAPTER 8 SYNCHRONOUS SEQUENITAL CIRCUITs proposed FSM to ensure that device 3 will get serviced, such that if it raises a request, the devices i and 2 will be serviced only once before the device 3 is granted its request. 8.39 Write VHDL code for the FSM designed in problem 8.38

Explanation / Answer

here we are having 4 inputs

1. reset

2. D1 to select device1

3. D2 to select device2

4. D3 to select device3

and having 3 outputs

G1,G2,G3

and 4states

1.idle

2.gnt1

3.gnt2

4.gnt3

library ieee;
use IEEE.std_logic_1164.all;

entity statefsm is
port (clk : in std_logic;
reset : in std_logic;
   D1 : in std_logic;

   D2 : in std_logic;
   D3 : in std_logic;
G1 : out std_logic;

G2 : out std_logic;
G3 : out std_logic;
);
end statefsm;

architecture behavioral of statefsm is

type state_type is (idle, gnt1, gnt2, gnt3);

signal current_s,next_s: state_type;
begin

process (clk,reset)
begin
if (reset='1') then
current_s <= idle;

elsif (rising_edge(clk)) then
current_s <= next_s;

end if;
end process;

--state machine process.
process (current_s,D1,D2,D3)
begin
case current_s is
when idle =>  
     if (D1 =’0’ ) and (D2 =’0’) and (D3=’0’) then
G1 <= '0';

G2 <= '0';

G3 <= '0';
next_s <= idle;
elsif ( D1 =’1’) then
   G1 <= '1'; G2<=’0’ ;G3<=’0’;
   next_s <= gnt1;
   elsif ( D1 =’0’) and (D2=’1’) then
   G2 <= '1'; G1<=’0’ ; G3<=’0’;
   next_s <= gnt2;
   elsif ( D1 =’0’) and (D2=’0’) and (D3=’1’) then
   G3 <= '1'; G2<=’0’; G1<=’0’;
   next_s <= gnt3;
     end if;

when gnt1 =>

if(D1=’1’) then

G1=’1’; G2<=’0’ ;G3<=’0’;

next_s <=gnt1;

elsif (D1=’0’) and (D2=’1’) then

G2 <= '1'; G1<=’0’ ; G3<=’0’;
   next_s <= gnt2;
   elsif ( D1 =’0’) and (D2=’0’) and (D3=’1’) then
   G3 <= '1'; G2<=’0’; G1<=’0’;
   next_s <= gnt3;

elsif ( D1 =’0’) and (D2=’0’) and (D3=’0’) then
   G3 <= '0'; G2<=’0’; G1<=’0’;
   next_s <= idle;

     end if;

when gnt2 =>

if(D2=’1’) then

G2=’1’; G1<=’0’ ;G3<=’0’;

next_s <=gnt2;

elsif (D2=’0’) and (D3=’1’) then
   G3 <= '1'; G2<=’0’; G1<=’0’;
   next_s <= gnt3;

elsif (D2=’0’) and (D3=’0’) then
   G3 <= '0'; G2<=’0’; G1<=’0’;
   next_s <= idle;

     end if;

    when gnt3 =>

if(D3=’1’) then

G1=’1’; G2<=’0’ ;G3<=’1’;

next_s <=gnt3;

elsif (D3=’0’) then
   G3 <= '0'; G2<=’0’; G1<=’0’;
   next_s <= idle;

     end if;

end case;
end process;

end behavioral;

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