Create a new Quartus II project and develop the VHDL code to create the multiple
ID: 2082388 • Letter: C
Question
Create a new Quartus II project and develop the VHDL code to create the multiplexer-decoder circuit shown below. Your code should select either Swa or SWb BCD inputs and display it as a decimal number on the 7-segment display output. State a VHDL entity declaration and architecture body Use STD_LOGIC_VECTOR type to fine inputs and output. You're not required to download your design onto an FPGA. You are, however, required to simulate it to show its proper operation. Cover page Copy and paste VHDL code (code should include comments) Simulation results showing correct implementation of the circuit Copy of circuitry displayed in the RTL viewerExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sevensegmemnt is
port (
clk : in std_logic;
sw : in std_logic_vector(3 downto 0);
segmemnt: out std_logic_vector(6 downto 0)
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of sevensegmemnt is
begin
process (clk,sw)
BEGIN
if (clk'event and clk='1') then
case sw is
when "0000"=> segmemnt <="0000001"; -- '0'
when "0001"=> segmemnt <="1001111"; -- '1'
when "0010"=> segmemnt <="0010010"; -- '2'
when "0011"=> segmemnt <="0000110"; -- '3'
when "0100"=> segmemnt <="1001100"; -- '4'
when "0101"=> segmemnt <="0100100"; -- '5'
when "0110"=> segmemnt <="0100000"; -- '6'
when "0111"=> segmemnt <="0001111"; -- '7'
when "1000"=> segmemnt <="0000000"; -- '8'
when "1001"=> segmemnt <="0000100"; -- '9'
when others=> segmemnt <="1111111";
end case;
end if;
end process;
end Behavioral;
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