(1) give some reasons on why verilog functions are needed (2). write a verilog f

Question

(1) give some reasons on why verilog functions are needed

(2). write a verilog function that will return the max of two 4 bits reg variables

(3). true and false

level sensitive latch can be described using an if statement.

verilog events have no time duration and hold basic values.

up to 3 delays can be specified for Verilog builtin 3-state gates. The smallest of the three applies to transition to X.

procedural continuous assignment assign values to register variables.s

UDP supports 3-state gate.

timing control is allowed in a function description.

2’b01 is false in a Verilog conditional expression.

2’b00 is true in a Verilog conditional expression.

procedural blocks can be self-triggered.

when a high voltage is applied across an anti-fuse, its resistance changes from high to low.

Explanation / Answer

1). Functions describe combinational logic, and by do not generate latches. Thus an if without an else will simulate as though it had a latch but synthesize without one. It is a good practice to code functions so they would not generate latches if the code were used in a procedure.
Functions are a good way to reuse procedural code, since modules cannot be invoked from a procedure.

2).

Function [3:0] f_max;

f_max = {out};

endfunction

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