In this lab, you are asked to implement and simulate F = AB + B\'C circuit in VH

Question

In this lab, you are asked to implement and simulate F = AB + B'C circuit in VHDL using www.edaplayground.com or similar. This assignment is to be completed in the groups from Lab 2 or you may great a new group of two. Each group is expected to complete the lab independently. Submit the following to me, with descriptions of each section: Schematic, labeled with the signals, ports and entities to be used. Labels must match your implementation. VHDL design and testbench files, using structural programming. Simulation output and a comparison with expected output.

Explanation / Answer

DESIGN:

-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity logic_imp is                  
   port( A, B, C : in std_logic;
            F : out std_logic);
end andGate;

--FUNCTIONAL DESCRIPTION
architecture func of logic_imp is
begin
F <= A and B;      
end func;

TESTBENCH:

-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

--ENTITY DECLARATION: no inputs, no outputs
entity logic_imp_tb is
end logic_imp_tb;

-- Describe how to test the logic_imp
architecture tb of logic_imp_tb is
   --pass logic_imp entity to the testbench as component
   component logic_imp is  
   port( A, B, C : in std_logic;
            F : out std_logic);
   end component;
  
   signal inA, inB, inC, outF : std_logic;
begin
   --map the testbench signals to the ports of the logic_imp
   mapping: logic_imp port map(inA, inB, inC, outF);

   process
   begin
      --TEST 1
      inA <= '0';
      inB <= '0';
      wait for 15 ns;

      --TEST 2
      inA <= '0';
      inB <= '1';
      wait for 15 ns;

      --TEST 3
      inA <= '1';
      inB <= '1';
      wait for 15 ns;

   end process;
end tb;

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