The gate comprises a circular metal electrode of 1.0 mm in diameter. The substra

Question

The gate comprises a circular metal electrode of 1.0 mm in diameter. The substrate is silicon (Relative permittivity 11.8) of unknown doping type and concentration, while the dielectric is silicon dioxide (relative permittivity 3.9) of unknown thickness tox( we calculated as 88.8nm).

frequency (100Khz) C-V curve of the MOS capacitor. Gate bias Vg is 9 V.

I need help for part 4, how do i find the doping concentration of the substrate? i have alrdy found the thickness of the oxide as 8.88nm

External bias (BNC connector at the back) Vg oxide High f 100kHz 9V Si substrate Low OO MOS capacitor DVM LCZ meter Figure 2.2: Schematic of circuit for measurement Recommended Measurement Parameters Frequency: 100 kHz Level: 50 mV Circuit: Auto A reading: C Breading: (not important Bias: Toggle to turn on extemal bias (BNC connector at the back of the meter) Test Fixture: Low connected to substrate, High connected to top gate. 1. Either manually plot (on graph paper) or print out (f you are using Excel the CV plot. Note the device ID on your plot. 2. On your plot, identify and label the accumulation, depletion, and strong inversion regimes 3. Is the substrate n-type or p-type? Explain. 4. Determine the thickness of the oxide (in nm), and the doping concentration of the substrate (in cm Show your working. You can use Excel or a programmable calculator to work out the doping concentration. 5. Sketch and label (as in part 2 above) the CV plot of a MOS capacitor with the same doping concentration, but of opposite type of dopant Assume that the gate metallization remains the same. Compared to your experimental device, how would the flat-band voltage be different? Explain.

Explanation / Answer

According to the asker

oxide thickness, Tox = 8.88 nm

relative permittivity, eox = 3.9

free space permittivity, e0 = 8.85 x 10-12

Gate Voltage, Vg = 9 V

First off all i want to say that as the C-V curve shows that the lower frequency is situated in the negative gate voltage region therefore, substrate is n-type.

Substrate material is silicon therefore,

relative permittivity, esi = 11.8xe0 = 1.044x10-10

PHISi = Affinity+Eg/2

now here i have considered

Affinity = 4.05

Eg = 1.12

PHISi = 4.05+1.12/2 = 4.05+0.56 = 4.61

Oxide Capacitor, Cox = (eox.e0)/Tox = 3.887 x 10-3

the depletion width due to the gate can be express by given formula

Wdep = SQRT[(2xesixPHISi)/qNd]

Vg = Vfb + PHISI+[(qNd/Cox)Wdep]

Now puth the value of Wdep into the above equation:

Vg = Vfb + PHISI+[(qNd/Cox)xSQRT[(2xesixPHISi)/qNd]]

Vg = Vfb + PHISI+SQRT[2xesixPHISixqNd]/Cox

Now if we consider energy band are flat then gate voltage is equal to flat band voltage

Vg = Vfb under flat band condition

PHISI = -SQRT[2xesixPHISixqNd]/Cox

PHISI x Cox= -SQRT[2xesixPHISixqNd]

Now taking square on both side

(PHISI x Cox)2 = 2xesixPHISixqNd

[PHISI x (Cox)2]/2xesixq = Nd

Nd = (4.61 x 3.887 x 10-3 x 3.887 x 10-3 )/2 x 1.044x10-10 x 1.6 x 10-19

Nd = (69.651 x 10-6)/3.3408 x 10-29

Nd = 20.84 x 1024 = 2.084 x 1025 /m3

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