We wish to design ALU hardware for a new MIPS R-type instruction called not spec

Question

We wish to design ALU hardware for a new MIPS R-type instruction called not specified as: not $rd, $zero, $rt which results in: $rd leftarrow (bitwise complement of $rt). Since the logical NOT operation takes only one operand, in this implementation the input is provided as $rt, the output is placed $rd, and the contents of the middle field are always provided as "$zero" by the programmer so that $rs=$zero. Then, one way to implement this instruction would be to modify the subtract unit as shown below. Assume the encoding specified in the table to answer the questions below: Starting with the bits of the funct field, explain in a few sentences how this hardware could execute a not $rd, $zero, $rt instruction. Starting with the bits of the funct field, explain in a few sentences how this hardware could execute a sub $rd, $rs, $rt instruction.

Explanation / Answer

9.1) To execute not, the input to funct is 111111 for which output line number 63 is logic 1 for 6:64 decoder. That makes output of OR gate go high. Now this output is further connected to one input of all XOR gates. In XOR gate if single input is logic 1 the output is complement of second input. Hence output of all XOR gates will be NOT of input $rt. With $rs being equal to all zeros, output of adder will be $rd = NOT ($rt).

9.2) Now to execute SUB, the input to funct is 100010 for which output line number 34 is logic 1 for 6:64 decoder. That makes output of OR gate go high. Now this output is further connected to one input of all XOR gates. This gives complement of $rt as explained in NOT function. Now also note that carry input to adder is coming from output line number 34 which is logic 1. Hence C0 = 1.

With this, Adder will perform $rs + NOT($rt) + 1. This gives output that is subtraction of $rs and $rt in 2's complement. (Initial carry of logic 1 is required to get 2's complement form for $rt which is NOT($rt) +1. )

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