PLEASE SHOW THE CODE Verilog or VHD code Design and construct a synthesizable Fi

Question

PLEASE SHOW THE CODE Verilog or VHD code

Design and construct a synthesizable Finite State Machine and Datapath which computes the greatest common denominator (GCD) of two numbers ( two 4-bit) numbers and output the binary value of the greatest common divisor of those two numbers.

Your design will consist of two components - the controller and the datapath. The controller is to be a pure FSM. The datapath operates based on signals generated by the controller FSM - it should have no independent controlling logic. ((datapath must be constructed structurally))

Use the GCD algorithm to help you with the code

Explanation / Answer

ANSWER:

The design is broken down into 2 modules - subtractor and the main control logic. The subtractor apart from subtracting the inputs also, gives out responses to the controller asking the controller to swap it's inputs and also tells if finding the GCD is completed or not. Based on these outputs, the controller state machine behaves accordingly.

module subtract (input bit [3:0] a, b, output bit [3:0] op, output bit gcd_done, swap_en);
assign op = a - b;
assign gcd_done = |b;
assign swap_en = (b < op);
endmodule

module gcd_ctl (
input bit swap_en, input bit gcd_done, input bit clk, input bit rst, input bit [3:0] A,B,sub_op ,
   output bit [3:0] sub_a, sub_b);

   bit [1:0] cur_st, nxt_st;

   always @ (posedge clk or posedge rst)
   if (rst) cur_st <= 2'b00;
   else cur_st <= nxt_st;

   always @ (*) begin
   case (cur_st)
   2'b00 : nxt_st = 2'b01;
   2'b01 : begin
   if (gcd_done) nxt_st = 2'b00;
       else nxt_st = 2'b01;
       end
   default : nxt_st = 2'b00;
   endcase
   end

   assign sub_a = (cur_st==2'b00) ? A : swap_en ? B : sub_op;
   assign sub_b = (cur_st==2'b00) ? B : swap_en ? sub_op : B;

endmodule

module GCD (input bit [3:0] A, B, output bit [3:0] RES, output bit done, input bit clk, rst);

bit [3:0] sub_op, sub_a, sub_b;
bit swap_en, gcd_done;

gcd_ctl CTL (
.swap_en (swap_en), .gcd_done (gcd_done), .clk (clk), .rst (rst), .A (A), .B (B), .sub_op (sub_op),
   .sub_a (sub_a), .sub_b (sub_b));

subtract SUB   
(.a (sub_a), .b (sub_b), .op (sub_op), .gcd_done (gcd_done), .swap_en (swap_en));

endmodule  
      

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