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Use RTL to create an ALU that operates on 4-bits 2\'s complememnt numbers. The o

ID: 2081291 • Letter: U

Question

Use RTL to create an ALU that operates on 4-bits 2's complememnt numbers. The op input specifies the ALU operations as follows:

2'b00: Y = A+B+Cin;

2'b01 : Y = A-B;

2'b10: Y = A xor B;

2'b11: Y = -b;

outputs also include carry out (cout), overflow detection (overflow), and zero detection (zero). If the output pertiant to the operation performed they can be consudered dont care cases.

the module interface should be used:

module ALU(output [3:0] Y, output cout, ouyput overfolw, output zero,

input [3:0] A,B input cin, input [1:0] op);

Write a Testbench that instantiates your module from above and demenostrates correct operatioans.

USe $monitor, $display, $strobe to print current simulation time and valuesof the input and output.

Explanation / Answer

// Design module for the ALU operation

module ALU
(
   output reg [3:0] Y,
   output reg cout, overflow, zero,
   input [3:0] A, B,
   input cin,
   input [1:0] op
);

// Functionality of the module
always @ (A, B, cin, op)
begin
   case (op)
       2'b00 : {cout, Y} = A + B + cin;
       2'b01 : {cout, Y} = A - B;
       2'b10 : Y = A ^ B;
       2'b11 : Y = (~B) + 1'b1;
   endcase
end

// Flags Generation
always @ (A, B, Y, cout)
begin
   if (Y == 4'd0)
       zero = 1'b1;

else

zero = 1'b0;

overflow = 1'b0;

if((op==2'b00) || (op == 2'b10))
   if ((A[3] == B[3]) && (Y[3] != cout))
       overflow = 1'b1;
end

endmodule


// Testbench for the ALU design above

module top;

wire [3:0] Y;
wire cout, overflow, zero;
reg [3:0] A, B;
reg cin;
reg [1:0] op;

// Instantiation of the module
ALU m1 (Y, cout, overflow, zero, A, B, cin, op);

integer i;

initial
begin
   $monitor ("A = %b, B = %b, cin = %d, op = %b, Y = %b, cout = %b, overflow = %b, zero = %b",
       A, B, cin, op, Y, cout, overflow, zero);

   for (i = 0; i < 4 ; i = i + 1)
   begin
       op = i;
       A = 4'b1001;
       B = 4'b0101;
       cin = 1'b1;
       #10;
   end

   #10;

   for (i = 0; i < 4 ; i = i + 1)
   begin
       op = i;
       A = 4'b1111;
       B = 4'b1111;
       cin = 1'b1;
       #10;
   end

   #10;

   for (i = 0; i < 4 ; i = i + 1)
   begin
       op = i;
       A = 4'b1101;
       B = 4'b0011;
       cin = 1'b0;
       #10;
   end

   #10;
   for (i = 0; i < 4 ; i = i + 1)
   begin
       op = i;
       A = 4'b0110;
       B = 4'b1100;
       cin = 1'b0;
       #10;
   end
end

endmodule

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