Many modern digital designs have independent clock domains. While the logic elem

Question

Many modern digital designs have independent clock domains. While the logic elements within each domain are synchronous with each other, there is no timing relationship between domains. in the circuit shown below, registers A and B are clocked by clk1 and clk2 that each has arbitrary (and unrelated to each other) frequencies. Explain whether it is possible to guarantee setup/hold time criteria on in2 (relative to clk2) for flip-flop B. What happens to the delay (i.e., t_clk, q) of the second flip-flop when you get an input that violates its setup/holds time? Your friend has come up with the alternative circuit shown that they claim will allow us to correctly transfer data from the clk1 domain to the clk2 domain. Under what condition will this circuit robustly achieve this goal? the plot below shows the Clk-Q delay as a function of arrival time difference between D and CLK inputs of flip-flops B and C. Assuming that the flip-flop has setup and hold times of 10ps, an of 40ps (as indicated in the plot below), and that the Clk-Q of the flip-flop increases by a factor of e for every factor of 2 reduction in |t_D-Clk| below 10ps (e.g., t_clk-q = e middot 10ps for |t_D-Clk| = 5ps), if clk2 has a period of 1ns, how small can the |t_D-Clk| for in2 be and still ensure that the circuit works robustly?

Explanation / Answer

(a) it is based on the clock periods of two clocks. There is a chance of setup and hold violation due to multi clock delays between transmit and receive edge i.e., use of multiple clocks, the data transmitted with clk1 and data received with clk2 . so violation possible at the time where posedges of two clocks met.

(b) if it causes setup and hold violation the delay of second flip flop is greater than (clock period - setup time - combinatorial delay ) . so to avoid violation time period-setup time must be greater than combinatorial delay + flip flop delay.

In case of hold analysis second flop delay should be greater than hold delay- combinatorial delay

(c) it is case of multi cycle paths but above thing is multi clock delays.

Related Questions

Navigate

• Browse (All)
• Browse M
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.