Given an MIPS instruction: Label: beq $s0, $s1, Label. Assume the processor is t

Question

Given an MIPS instruction: Label: beq $s0, $s1, Label.

Assume the processor is the same as the one shown in Figure 4.24 in the textbook.

a) What is the value of control bit “ALUSrc”? What operation is the ALU configured to perform?

b) What value is the output of “Shift left2” module?

Shift Jump address 131-01 r instruction 125 left 2 26 28 PC 4 131-281 Add Add result Shift RegDst left 2 Jum Branch Mem Read Instruction 31-261 MemtoReg Control ALUOp MemWrite ALUSrc RegWrite nstruction 125-211 Read Read PC address register 1 Read Instruction 120-16) Read data 1 H Zero register 2 Instruction ALU ALU 131-0] Read M Write Address result data 2 Instruction nstruction [15-11] X register memory Write data Registers Write Data memory Sign 32 16 Instruction t15-01 ALU extend control Instruction 15-01

Explanation / Answer

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies (formerly MIPS Computer Systems, Inc.). The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations).MIPS32 and MIPS64 define a control register set as well as the instruction set.

Label: beq $s0, $s1, Label.(branch if equal)

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