Create an 8-bit Verilog counter module out of J/K flip-flops. Dene the top-level
ID: 2080853 • Letter: C
Question
Create an 8-bit Verilog counter module out of J/K flip-flops. Dene the top-level counter module with the following I/O signals:
inputs: mclk to MCLK, incr to BTN0, rst to BTN1; output: [7:0] Q to LD0-LD7
Use a generate loop to instantiate J/K ip-ops and build an eight-bit counter module. Below is my J/K flip-flop code.
module JKFF(
input j,
input k,
input clk,
output reg q
);
always @(posedge clk) begin
if(j==1'b0 && k==1'b1) begin
q <= 'b0;
end
else if(j==1'b1 && k==1'b0) begin
q<= 1'b1;
end
else if(j==1'b1 & k==1'b1) begin
q <= ~q;
end
end
endmodule
Explanation / Answer
To create 8-bit verilog counter module from J-K Flipflop we have to do pre-requisite -
Pull all the J&K high. Clock to the first Flip-flop. Connect the Q outputs directly to the clocks of consecutive Flip-Flops (If it's ~Clock input) Otherwise use ~Q output to clock.
Solutions to J/K Flip-flop code :
testjkflop.v
module main;
reg j,k,clk,rst;
wire q;
jkflop jk(j,k,clk,rst,q);
//Module to generate clock with period 10 time units
initial begin
forever begin
clk=0;
#5
clk=1;
#5
clk=0;
end
end
initial begin
j=0; k=0; rst=1;
#4
j=1; k=1; rst=0;
#40
rst=1;
#10
j=0; k=1;
#10
rst=0;
#10
j=1; k=0;
end
endmodule
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