Verilog comparator problem - Use the follow code Requirements 1: Expandable 2:Te
ID: 2080392 • Letter: V
Question
Verilog comparator problem - Use the follow code
Requirements
1: Expandable
2:Testbench for expandable
3: Using expandable to create an eight8(Bit)Comparator
Written in behavioral dataflow in verilog
the final code needs to use the right ports so a given testbench instantiates it correctly
Useful things I was provided with this picture to get an idea of what is going on; Note that A[3] is the MSB of A[3:0].
Explanation / Answer
Logic to get 8bit comparator using expandable 2bit comparator module.
To get an 8bit comparator from a 2bit. We need to go hierarchial. We need to compare A7 A6 and B7 B6 using a 2bit expandable comparator and then give the result to the next 2bit comparator that compares A5A4 and B5B4 and so on.
What we need to do.
The given 2bit code should be modified to 2bit expandable module.
Please find the code below
Thumb rule: If the previous bits of A are Greater than B then the whole A is grrater than B. So if IGT = 1 then OGRE = 1. similarly if previous bits of A are less than previous bits of B I.e, if ILT = 1 then OLES = 1.
So let's do an expandable 2 bit comparator
module two_bit_comparator(A,B,IGT,IEQ,ILT,OGRE,OEQU,OLES);
input [1:0] A,B;
input IEQ,IGT,ILT;
output reg OGRE,OEQU,OLES;
reg check;
always @ (A,B,IGT,ILT,IEQ)
begin
check = (IEQ || (!(IEQ || IGT || ILT)));\ at condition all the IGT, IEQ, ILT ARE 0
OGRE = IEQ?(A>B ? 1 : 0) : IGT;
OLES = IEQ ? (A<B ? 1 : 0) : ILS;
OEQU = IEQ ? (A=B ? 1 : 0) : 0;
end
endmodule
module eight_bit_comparator(A,B,IEQ,ILT,IGT,OEQ,OLT,OGT);
input [7:0] A,B;
input IEQ,ILT,IGT;
output OEQ,OLT,OGT;
two_bit_comparator c3 (.A({A[7],A[6]}),.B({B[7],B[6]}),.IEQ(IEQ),.ILT(ILT),.IGT(IGT),.OGRE(GTC3),.OEQU(EQC3),.OLES(LTC3));
two_bit_comparator c2 (.A({A[5],A[4]}),.B({B[5],B[4]}),.IEQ(EQC3),.ILT(LTC3),.IGT(GTC3),.OGRE(GTC2),.OEQU(EQC2),.OLES(LTC2));
two_bit_comparator c1 (.A({A[3],A[2]}),.B({B[3],B[2]}),.IEQ(EQC2),.ILT(LTC2),.IGT(GTC2),.OGRE(GTC1),.OEQU(EQC1),.OLES(LTC1));
two_bit_comparator c0 (.A({A[1],A[0]}),.B({B[1],B[0]}),.IEQ(EQC1),.ILT(LTC1),.IGT(GTC1),.OGRE(OGT),.OEQU(OEQ),.OLES(OLT));
endmodule
Note: The operator {} is used to group the bits. It is used above as the ports A and B are of size 2 bits.
Tst bench for 2bit comparator
module twobit_TST();
reg [1:0] A,B;
reg ILT,IGT,IEQ;
wire OEQ,OLT,OGT;
two_bit_comparator m1 (A,B,IGT,IEQ,ILT,OGRE,OEQU,OLES);
initial
begin
A = 0 ;
B = 0;
#5 {IGT,IEQ,ILT} = 3'b100;
#5 {IGT,IEQ,ILT} = 3'b010;
#5 {IGT,IEQ,ILT}= 3'b001;
#5
A = 3;
B = 2;
#5 {IGT,IEQ,ILT} = 3'b100;
#5 {IGT,IEQ,ILT} = 3'b010;
#5 {IGT,IEQ,ILT}= 3'b001;
#5
A = 2 ;
B = 3;
#5 {IGT,IEQ,ILT} = 3'b100;
#5 {IGT,IEQ,ILT} = 3'b010;
#5 {IGT,IEQ,ILT}= 3'b001;
end
endmodule
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