Below is a code for a signed adder, whose ports are all of type STD_LOGIC_VECTOR

Question

Below is a code for a signed adder, whose ports are all of type STD_LOGIC_VECTOR (industry standard). Analyze it and answer the questions below. (Suggestion: see example 3.9.)

d) Do you expect any problems in the type conversion of line 16? Why?

e) Present a solution to remedy the problem in (d) by including additional computing steps in the code.

f ) Present another solution for the problem in (d), this time by replacing one of the de- clared packages.

g) Present one more solution for that problem, now using a ‘‘qualified’’ expression. h) Finally, in your opinion, what is the recommended code for such a signed adder?

Explanation / Answer

d) Yes. The problem arises because the '+' operator is overloaded in the std_logic_arith library for the given type of arguments to produce results of different types.

L and R denote the arguments to the left and right of the +. In this case a_sig and b_sig. The result of a_sig + b_sig can either be of the type signed or std_logic_vector. Hence we get an error.

e)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

------------------------------------------------
ENTITY signed_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END ENTITY;
------------------------------------------------
ARCHITECTURE arch OF signed_adder IS
SIGNAL a_sig, b_sig, c_sig: SIGNED(3 DOWNTO 0); --declare a new signal c_sig
BEGIN
a_sig <= signed(a);
b_sig <= signed(b);
c_sig <= a_sig + b_sig; --initialising c_sig
sum <= STD_LOGIC_VECTOR(c_sig);
END ARCHITECTURE;

f)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all; -- Package replaced
------------------------------------------------
ENTITY signed_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
------------------------------------------------
ARCHITECTURE arch OF signed_adder IS
SIGNAL a_sig, b_sig : SIGNED(3 DOWNTO 0);
BEGIN
a_sig <= signed(a);
b_sig <= signed(b);
sum <= STD_LOGIC_VECTOR(a_sig+b_sig);
END ARCHITECTURE;

g)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
------------------------------------------------
ENTITY signed_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
------------------------------------------------
ARCHITECTURE arch OF signed_adder IS
SIGNAL a_sig, b_sig : SIGNED(3 DOWNTO 0);
BEGIN
a_sig <= signed(a);
b_sig <= signed(b);
       sum <= STD_LOGIC_VECTOR'(a_sig+b_sig); -- Type qualified
END ARCHITECTURE;

h)

Changing the package to numeric_std is preferred. std_logic_arith, etc. were packages written by Synopsis and included in their tools' version of the ieee library, without the approval of the ieee standardization body. Since there is no standard governing it, it is subject to change at any time. numeric_std is an ieee standard packages, located in the official version of the ieee library, and their behavior is governed by the standard, so compatibility is assured.

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