Add plenty of comments to prove you know what code is doing. Save this file. Do

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Add plenty of comments to prove you know what code is doing. Save this file. Do not compile yet! Open a new VHDL file then complete the code below the seven segment decoder. LIBRARY ieee. Use ieee.std.logic_1164.ALL; use ieee.std_logic_arith.all; use ieee_std_logic_unsigned all; ENTITY seven IS port {sum in std_logic vector(3 downto 0); HEX out std_logic_vector(6, downto 0)}; END seven; ARCHITECTURE beh OF seven IS BEGIN With sum select HEX "1000000" when "0000", -0 "_____" when "0001", -1 "_____" when "0010", -2 "_____" when "0011", "_____" when "0100", "_____" when "0101", "_____" when "0110", "_____" when "0111", "_____" when "1000", "_____" when "1001", "_____" when "1010", -a "_____" when "1011", -b "_____" when "1100", "_____" when "1101", "_____" when "1110", "_____" when "1111", -1 "1111111" when others. END beh. Add plenty of comments to prove you know what the code is doing.

Explanation / Answer

Basic Issues and Simulation Semantics 1. VHDL: History and Main Features 2. Basic Constructs 3. An Example: Behavioral and Structural Models 4. Concurrent Statements 5. Signals and the Wait Statement 6. The VHDL Simulation Mechanism 7. The Delay Mechanism 8. Resolved Signals 9. VHDL for System Synthesis System Synthesis - VHDL Basics Fö 2 - 2 Petru Eles, IDA, LiTH VHDL History • The name: VHSIC Hardware Description Language • Important dates: - 1983: development started with support from US government. - 1987: adopted by IEEE as a standard (IEEE Std. 1076 - 1987). - 1993: VHDL’92 adopted as a standard after revision of the initial version (IEEE Std. 1076 - 1993). • Work is going on for the release of new revisions (e.g. including facilities for analog modeling and simulation). System Synthesis - VHDL Basics Fö 2 - 3 Petru Eles, IDA, LiTH Main Features • Supports the whole design process from high to low abstraction levels: - system and algorithmic level - Register Transfer (RT) level - logic level - circuit level (to some extent) • Suitable for specification in - behavioral domain - structural domain System Synthesis - VHDL Basics Fö 2 - 4 Petru Eles, IDA, LiTH Main Features (cont’d) • Precise simulation semantics is associated with the language definition: - specifications in VHDL can be simulated; - the simulation output is uniquely defined and independent of the tool (VHDL implementation) and of the computer on which the tool runs. • VHDL specifications are accepted by hardware synthesis tools. - Both the input and the output of the synthesis process are very often codified in VHDL. System Synthesis - VHDL Basics Fö 2 - 5 Petru Eles, IDA, LiTH Basic Constructs • The basic building block of a VHDL model is the entity. • A digital system in VHDL is modeled as an entity which itself can be composed of other entities. • An entity is described as a set of design units: - entity declaration - architecture body - package declaration - package body - configuration declaration • A design unit can be compiled separately. System Synthesis - VHDL Basics Fö 2 - 6 Petru Eles, IDA, LiTH An Example A four bit parity generator V

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