If an SRAM with t_AA = 30 ns, t_CE = 30 ns, t_OE = 10 ns, and t_OH = 10 ns (refe

Question

If an SRAM with t_AA = 30 ns, t_CE = 30 ns, t_OE = 10 ns, and t_OH = 10 ns (referenced from the negation of OE) is interfaced to the processor depicted in this timing chart, the read timing margin provided will be: (A) 10 ns (B) 20 ns (C) 30 ns (D) 40 ns (E) none of the above If an SRAM with t_AW = 30 ns, t_CW = 30 ns, t_IS = 20 ns, and t_IH = 0 ns is interfaced to the processor depicted in this timing chart, the write timing margin provided will be: (A) 10 ns (B) 20 ns (C) 30 ns (D) 40 ns (E) none of the above

Explanation / Answer

(17) Answer is 10ns, which is option (A) 10ns

Reason: As the reference is from the negation of OE so output read timing is at toe=toh=10ns

(18) Answer is 30ns, which is option (C) 30ns

Reason: As the SRAM is interfaced to processor, so write timing margin will be 30ns (taw=tcw)

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