Sketch a 2-input NOR gate with transistor widths chosen to achieve effective ris

Question

Sketch a 2-input NOR gate with transistor widths chosen to achieve effective rise and fall resistances equal to the inverter below (the widths of the inverter are shown in the figure). Assume the length of each transistor is set as 1. a =; b=; c=; d =; assume the nmos of the Inverter has resistance R and capacitance C. and the two PMOS of the NOR circuits share a common source drain Compute the rising and falling propagation delays of the NOR gate driving h identical NOR gates using the Elmore delay model. Rising propagation delay is _________ RC: falling propagation delay is _________ RC. assume the nmos of the Inverter has resistance R and capacitance C. and the two PMOS of the NOR circuits share a common source drain Compute the rising and falling contamination delays of the NOR gate driving h identical NOR gates using the Elmore delay model. Rising contamination delay is _________ RC: falling contamination delay is _________ RC.

Explanation / Answer

1). To Achieve the same effective rise and fall time as inverter the sizing of NOR gate is such that so for falling/rising it sees the same resistance as in case of inverter.

MOS added in series is same as having single transistor of length twice.

so Width of C and D are such that for rising they offer same resistance as in case of inverter

C = 4 , D=4.

For the sizing of A and B the, it is possible that only single transistor is on at a time so effective resistance must be same as inverter and when both are on then effective resistance are lower than the inverter so it is fine.

A=1 , B=1

Related Questions

Navigate

• Browse (All)
• Browse S
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.