Write a top level module to implement the circuit on an Altera FPGA board. a. Da
ID: 2079910 • Letter: W
Question
Write a top level module to implement the circuit on an Altera FPGA board.
a. Data input - switches 3:0
b. Select input - switches 5:4
c. Show switch states on the red leds
d. Show the mux output on the HEX0 seven segment display. Values shown will either be 0 or 1. Use a seven segment module. Use concatenation to form the four bit signal required by the seven segment module. assign {A, B, C, D} = { 3’b000, m}; where A, B, C, D are the 7 segment module inputs; m is the mux output
Can anyone please tell me what's wrong with my code?
1. 7 segment
module hex_7seg_bitwise(A,B,C,D,m);
//input A, B, C, D;
input wire A,B,C,D;
// 7 bit signal
output wire [6:0] m;
//connects switches with bus
assign m[0] = (~A&~B&~C&D)|(~A&B&~C&~D)|(A&B&~C&D)|(A&~B&C&D);
assign m[1] = (B&C&~D)|(A&C&D)|(A&B&~D)|(~A&B&~C&D);
assign m[2] = (A&B&~D)|(A&B&C)|(~A&~B&C&~D);
assign m[3] = (~B&~C&D)|(B&C&D)|(A&~B&C&~D)|(~A&B&~C&~D);
assign m[4] = (~A&D)|(~B&~C&D)|(~A&B&~C);
assign m[5] = (~A&~B&D)|(~A&~B&C)|(~A&C&D)|(A&B&~C&D);
assign m[6] = (~A&~B&~C)|(~A&B&C&D)|(A&B&~C&~D);
endmodule
2. 4X1 MUX
//Verilog structural description of a 4 to 1 multiplexer
module mux1to4(D,S,m);
input [1:0]S;//select input
input [3:0]D;// data input lines
output wire m;//output
//internal signal decleration
assign m = (~S[0]&~S[1]&D[0] )|(~S[0]&S[1]&D[1] )|(S[0]&~S[1]&D[2] )|(S[0]&S[1]&D[3]);
endmodule
3. Top-Level
//Verilog structural description of a four bit 4 to 1 multiplexer
module mux4to1_top(SW,S,m,LEDR,HEX0);
input [3:0]SW;// toggle switches
input [5:4]S;//select switches
output [5:0]LEDR;//red leds
output [6:0]HEX0;//7 segment display
output m;
assign LEDR[3:0]=SW[3:0];//
assign {A,B,C,D} = { 3'b000, m};
mux1to4 inst0(SW[3:0],S[5:4],HEXO);
endmodule
Explanation / Answer
please try running this one:
module hex_7seg_bitwise(A,B,C,D,m);
//input A, B, C, D;
input wire A,B,C,D;
// 7 bit signal
output wire [6:0] m;
//connects switches with bus
assign m[0] <= (~A&~B&~C&D)|(~A&B&~C&~D)|(A&B&~C&D)|(A&~B&C&D);
assign m[1] <= (B&C&~D)|(A&C&D)|(A&B&~D)|(~A&B&~C&D);
assign m[2] <= (A&B&~D)|(A&B&C)|(~A&~B&C&~D);
assign m[3] <= (~B&~C&D)|(B&C&D)|(A&~B&C&~D)|(~A&B&~C&~D);
assign m[4] <= (~A&D)|(~B&~C&D)|(~A&B&~C);
assign m[5] <= (~A&~B&D)|(~A&~B&C)|(~A&C&D)|(A&B&~C&D);
assign m[6] <= (~A&~B&~C)|(~A&B&C&D)|(A&B&~C&~D);
endmodule
2. 4X1 MUX
//Verilog structural description of a 4 to 1 multiplexer
module mux1to4(D,S,m);
input [1:0]S;//select input
input [3:0]D;// data input lines
output wire m;//output
//internal signal decleration
assign m <= (~S[0]&~S[1]&D[0] )|(~S[0]&S[1]&D[1] )|(S[0]&~S[1]&D[2] )|(S[0]&S[1]&D[3]);
endmodule
3. Top-Level
//Verilog structural description of a four bit 4 to 1 multiplexer
module mux4to1_top(SW,S,m,LEDR,HEX0);
input [3:0]SW;// toggle switches
input [5:4]S;//select switches
output [5:0]LEDR;//red leds
output [6:0]HEX0;//7 segment display
output m;
assign LEDR[3:0]<=SW[3:0];//
assign {A,B,C,D} <= { 3'b000, m};
mux1to4 inst0(SW[3:0],S[5:4],HEXO);
endmodule
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