I need a test bench in verilog for the following code. The inputs are 4 switches

Question

I need a test bench in verilog for the following code. The inputs are 4 switches that when turned on in binary order display the following on the seven segment display. Anything over 9 displays an E module display(input [3:0]s. output [6:0]seg); assign seg[0] = Tilde s[0]&s;[3]|s[1]& Tilde s[3]|s[0]&s;[2]? 1'b0:1'b1; assign seg[1] = Tilde s[0]&s;[1]&s;[2]|s[0]& Tilde s[1]& Tilde s[2] ? 1'b0:1'b1; assign seg[2] = s[0]& Tilde s[1]& Tilde s[2] |Tilde s[0]&s;[1]& Tilde s[2]& Tilde s[3] | Tilde s[0]&s;[1]&s;[2]&s;[3]? 1'b0:1'b1; assign seg[3] = s[0]&s;[2] |s[0]&s;[1]|s[1]& Tilde s[2]& Tilde s[3] ? 1'b0:1'b1; assign seg[4] = Tilde s[1]&s;[2]|s[0]& Tilde s[3]|s[0]&s;[2]|s[1]& Tilde s[2]&s;[3] ? 1'b0:1'b1; assign seg[5] = s[2]& Tilde s[3]|s[1]& Tilde s[2] |s[0]& Tilde s[3] |s[0]&s;[2] |Tilde s[0]& Tilde s[1]&s;[3] ? 1'b0:1'b1; assign seg[6] = Tilde s[2]& Tilde s[3]|s[2]&s;[3] |s[1]& Tilde s[2] |s[0]& Tilde s[3] ? 1'b0:1'b1; end module|

Explanation / Answer

module tb ();

reg [3:0] s;

wire [6:0] seg;

display inst (.s(s), .seg(seg));

initial begin

s = 0;

#100;

s = 1;

#100;

s = 2;

#100;

s = 3;

#100;

s = 4;

#100;

s = 5;

#100;

s = 6;

#100;

s = 7;

#100;

s = 8;

#100;

s = 9;

#100;

s = 10;

#100;

s = 11;

#100;

s = 12;

#100;

s = 13;

#100;

s = 14;

#100;

s = 15;

#100;

end

endmodule

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