Design a VHDL module for each of the following circuits. Your solutions should i
ID: 2079026 • Letter: D
Question
Design a VHDL module for each of the following circuits. Your solutions should include
VHDL source code with comments. Assume positive edge trigger for all flip-flops. Use a
text editor that will replace tabs with spaces for all your VHDL code.
4. Sixteen Bit Register with Load and Shift Inputs: clock, load, din (16-bits), shift Outputs: 16-bit register value Implement all 16-bits in a single VHDL process. When the load signal is asserted, the register should synchronously load the value of din. When shift '1', bit 15 should load zero and bits (14:0) should be assigned to the previous value of bits (15:1).Explanation / Answer
library IEEE;
use IEEE.std_logic_1164.all;
entity bit16_load_and_shift is
port(din: IN std_logic_vector (15 downto 0); -- declare that din is a 16bit input
load: IN std_logic;
clock: IN std_logic;
shift: IN std_logic;
output: OUT std_logic_vector(15 downto 0)); ---- declare that output is a 16bit output
end bit16_load_and_shift; -- entity is ended
architecture behavior of bit16_load_and_shift is
begin
process (clock)
begin
if (rising_edge (clock)) then -- if raising edge of the clock and load is =1 then only input is loaded into the register and display them to the output
if(load = '1') then
output <= din;
end if;
end if;
end process;
process (clock)
begin
if (rising_edge(clock)) then -- if raising edge of the clock and shift is =1 the it shifts by one bit the msb bit loaded with 0 and remaining bits are right shifted by one position
if(shift ='1') then
output <= '0' & output(15 downto 1);
end if;
end if;
end process;
end behavior;
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