Design in VHDL a 2\'s complement multiplier which takes two 4-bit 2\'s complemen
ID: 1996107 • Letter: D
Question
Design in VHDL a 2's complement multiplier which takes two 4-bit 2's complement numbers, "a" and "b" and creates an 8-bit 2's complement output "m". This should be done in part by implementing 3 adder circuits, as shown in the figure below. The two adders signified by the red boxes should compute in parallel, and the outputs of the two red boxes (pp0 and pp1) should be registered. Those two registered values should be finally added together to create the final output "m". You may use the arithmetic method to implement your adders. Be careful to only use minimally sized computational units and signal vectors, points will be deducted if you have an implementation which does computation or transmits a signal which is always 0.Explanation / Answer
library BITLIB;
use BITLIB.bit_pack.all;
entity multiplier4X4 is
port (Clock, St: in bit;
Mtplier,Mcand: in bit_vector(3 downto 0);
De: out bit);
end multiplier4X4;
architecture behave of multiplier4X4 is
signal State: integer range 0 to 9;
signal ACCUM: bit_vector(8 downto 0);
alias M: bit is ACCUM(0);
begin
process
Begin wait until Clock = ‘1’;
case State is
when 0=>
if St='l' then
ACCUM(8 downto 4) <= “0000”;
ACCUM(3 downto 0) <= Mplier;
State<= 1;
end if;
when 1 I 3 I 5 I 7 =>
if M = ‘1’ then
ACCUM(8 downto 4) <=add4(ACCUM(7 downto 4),Mcand,’(Y);
State <= State+1;
else
ACCUM <= ‘O’ & ACCUM(8 downto 1);
State <= State+2;
end if;
When 2 |4|6|8=>
ACCUM<= ‘0’ & ACCUM(8 downto 1);
State <= State+1;
when9=> State<=O;
end case;
end process;
Done <='1' when State =9 elese '0';
end behave;
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