Use the given figure to answer the following questions Inverter: tpdinv = 1. 0 n

Question

Use the given figure to answer the following questions Inverter: tpdinv = 1. 0 nsec OR Gate: tpdNAND = 2. 0 nsec AND Gate: tpdAND = 2. 5 nsec Flip-flop: tpdFF = 2. 0 nsec, tsetup = 1. 0 nsec, thold = . 5 nsec Determine the critical path (indicate both the delay time and the sequence of devices that makes up the critical path). Determine the shortest clock period under which the circuit can operate. Determine the fastest clock frequency under which the circuit can operate. Assuming the circuit is operating at 145 MHz, what are the setup and hold time margins?

Explanation / Answer

a. sequence = S1-N0-So-N1

delay = 2+1+0.5+2.5+1+2+1+0.5+2.0 = 12.5nsec

b) shortest clock periio = 0.5 nsec

c) 1/ 2.5 nsec

d)step margin = 2 nsec

hold margin = 0.5 nsec

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