1. Write a VHDL code in data flow style to implement the circuit in Figure 1 usi
ID: 1847490 • Letter: 1
Question
1. Write a VHDL code in data flow style to implement the circuit in Figure 1 using one selected signl assignment. Further, develop a testbench that applies all input combinations. Submit VHDL codes for the circuit and test bench and the output waveform.
2. Write a VHDL code in behavioral style to implement the circuit in Figure 1 using one if statement. Further, develop a testbench that applies all input combinations. Submit VHDL codes for the circuit and testbench and the output waveform.
3. Write a VHDL code in structural style to implement the circuit in Figure 1. Further, develop a testbench that applies all input combinations. Submit VHDL codes for the circuit and testbench and the output waveform.
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
entity fun is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
C,B,D,A : in STD_LOGIC;
O: out STD_LOGIC);
end fun;
architecture Behavioral of fun is
begin
O=((I0' and I1')and A) or ((I0 and I1') and B) or ((I0' and I1) and C) or ((I0 and I1) and D)
end Behavioral;
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