I can offer more points if it sparks anyones interest. Total value depending if

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I can offer more points if it sparks anyones interest. Total value depending if I figure out where I went wrong.

will give more points if you help!

This flip-flop is sometimes called a transparent latch, because while Enable is high, the data outputs follow the data input. If two data-type latches are connected as above (right), the result is an edge-triggered latch. In this configuration, two transparent D-type latches are connected in tandem. The enable input, when low, causes the first flip-flop to be in the transparent state, and the second flip-flop to be locked. When Enable goes high, the second flip flop becomes transparent first, then after a brief delay the first flip-flop becomes locked. The output of the second flip-flop will show the locked output of the first. Even though the second latch is in its transparent state, the data on the output will not change, because the first latch is locked. When enable goes low again, the second flip-flop becomes locked first, then the first becomes transparent. The data output will remain unchanging, because now the second flip-flop is locked. The only time new data can be stored in the circuit, is during the brief moment when the enable input goes from low to high. This transition is referred to as a rising clock edge, and so this tandem latch configuration is called a rising edge triggered latch. The two flip-flops and inverter can be enclosed by a box, and represented by a single symbol. The Enable input of the transparent latch is replaced by the clock pulse input. T(he edge-triggered latch is one of the central circuits in computer design.

Explanation / Answer

VHDL program for Master slave D flip flop comprises three stages

1] First, we define a NAND Gate entity

2] Second, we construct a D-latch entity using four NAND Gates.

3] Finally, we construct the master-slave D- flipflop using two D-latches and two inverters.

-- We first define a NAND Gate entity. Later we will construct the D-latch entity using this NAND Gate.---

library ieee;

use ieee.std_logic_1164.all;

entity nandGate is

   port(A, B : in std_logic;

           F : out std_logic);

end nandGate;

architecture nandFunc of nandGate is

begin

   F <= A nand B;

end nandFunc;

--*===================================== END NAND GATE

--Here we define the D-Latch entity. Observe that in the architecture

--section --the NAND Gate is used to build the structural core of the D---latch.---

library ieee;

use ieee.std_logic_1164.all;

entity D_latch is

   port(E, D : in std_logic;

       Q, notQ : out std_logic);

end D_latch;

architecture func of D_latch is

   component nandGate is

      port(A, B : in std_logic;

              F : out std_logic);

   end component;

   signal topWire, botWire, Qback, notQback : std_logic;

library ieee;

use ieee.std_logic_1164.all;

entity notGate is  

   port( inPort   : in std_logic;

         outPort : out std_logic);

end notGate;

architecture func of notGate is

begin

   outPort <= not inPort;

end func;

library ieee;

use ieee.std_logic_1164.all;

entity ms_Data_ff is

   port( clk, D : in std_logic;

        Q, notQ : out std_logic);

end ms_Data_ff;

architecture func of ms_Data_ff is

   --import the inverter entity as a component

   component notGate is   

      port( inPort : in std_logic;

           outPort : out std_logic);

   end component;

--import the D-latch entity as a component

   component D_latch is

      port(E, D : in std_logic;

          Q, notQ : out std_logic);

   end component;

signal invOut1, invOut2, Dout, dummy : std_logic;

begin

   G1: notGate port map(clk, invOut1);

   G2: notGate port map(invOut1, invOut2);

   G3: D_latch port map(invOut1, D, Dout, dummy);

   G4: D_latch port map(invOut2, Dout, Q, notQ);

end func;

Test Bench:

library ieee;

use ieee.std_logic_1164.all;

entity ms_Data_ff_tb is

end ms_Data_ff_tb;

----------------------

architecture tb of ms_Data_ff_tb is

   component ms_Data_ff is

      port(clk, D : in std_logic;

          Q, notQ : out std_logic);

   end component;

   -------------

   signal clk, D, Q, notQ : std_logic;

   -------------

begin

mapping: ms_Data_ff port map(clk, D, Q, notQ);

--concurrent processes

process

begin

   clk <= '1';

   wait for 15 ns;

   clk <= '0';

   wait for 15 ns;

end process;

process

   variable errCnt : integer := 0;

begin

-------------TEST 1

   D <= '0';

   wait for 67 ns;

   assert(Q = '0') report "Error 1" severity error;

   if(Q /= '0') then

      errCnt := errCnt + 1;

   end if;

----------TEST 2

   D <= '1';

   wait for 67 ns;

   assert(Q = '1') report "Error 1" severity error;

   if(Q /= '1') then

      errCnt := errCnt + 1;

   end if;

   -----------------SUMMARY

   if(errCnt = 0) then

      assert false report "Good" severity note;

   else

      assert true report "Bad" severity error;

   end if;

end process;

end tb;

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