please showe work A, B, C only A famous logic designer decided to quit teaching

Question

please showe work

A, B, C only

A famous logic designer decided to quit teaching again and make a fortune by licensing a circuit design, this time the one shown in Figure X6.70. Label the inputs and outputs of the circuit with appropriate signal names, including active-level indications. What does the circuit do? Be specific and account for all inputs and outputs. Draw the logic symbol that would go on the data sheet of this circuit. Write an ABEL or behavioral VHDL or Verilog program for the circuit. With what standard building blocks does the new circuit compete? Do you think it would be successful as an MSI part?

Explanation / Answer

ibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -------------------------------------------------------------------------------- ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; -------------------------------------------------------------------------------- entity NAND1 is     Port ( X : in std_logic;            Y : in std_logic;            F : out std_logic); end NAND1; architecture Behavioral of NAND1 is begin Process (X,Y) begin                         F <= X NAND Y;             end process; end Behavioral; entity AND1 is     Port ( X : in std_logic;            Y : in std_logic;            F : out std_logic); end AND1; architecture Behavioral of AND1 is begin Process (X,Y) begin                         F <= X AND Y;             end process; end Behavioral; entity AND1 is     Port ( X : in std_logic;            Y : in std_logic;            F : out std_logic); end AND1; architecture Behavioral of AND1 is begin Process (X,Y) begin                         F <= X AND Y;             end process; end Behavioral;
entity NOT1 is     Port ( X : in std_logic; F : out std_logic); end NOT1; architecture Behavioral of NOT1 is begin Process (X) begin                         F <= NOT X ;             end process; end Behavioral; entity NOT1 is     Port ( X : in std_logic; F : out std_logic); end NOT1; architecture Behavioral of NOT1 is begin Process (X) begin                         F <= NOT X ;             end process; end Behavioral;
entity main_circuit is     Port ( a,b,c,d,e,f : in std_logic;    g, : out std_logic_vector(7 downto 0)); end main_circuit; entity main_circuit is     Port ( a,b,c,d,e,f : in std_logic;    g, : out std_logic_vector(7 downto 0)); end main_circuit; architecture Behavioral of main_circui is
signal h,i,j,k : std_logic;

component NAND1       Port ( X : in std_logic;

           Y : in std_logic;            F : out std_logic); end component;

component AND1       Port ( X : in std_logic;

           Y : in std_logic;            F : out std_logic); end component;

component NOR1       Port ( X : in std_logic;

           Y : in std_logic;            F : out std_logic); end component;

  Port ( X : in std_logic;

F : out std_logic); end component;

begin

process(a,b,c,d,e,f )

u1:NOR1 portmap(a,b,h);

u2:NOT1 portmap(c,i);

u3:NOT1 portmap(d,j);

architecture Behavioral of main_circui is
signal h,i,j,k : std_logic;

component NAND1       Port ( X : in std_logic;

           Y : in std_logic;            F : out std_logic); end component;

component AND1       Port ( X : in std_logic;

           Y : in std_logic;            F : out std_logic); end component;

component NOR1       Port ( X : in std_logic;

           Y : in std_logic;            F : out std_logic); end component;

  Port ( X : in std_logic;

F : out std_logic); end component;

begin

process(a,b,c,d,e,f )

u1:NOR1 portmap(a,b,h);

u2:NOT1 portmap(c,i);

u3:NOT1 portmap(d,j);

           Y : in std_logic;            F : out std_logic);            Y : in std_logic;            F : out std_logic);            Y : in std_logic;            F : out std_logic); F : out std_logic);

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