Modify the text file from so that the counter only counts odd numbers: 001, 011,
ID: 1846220 • Letter: M
Question
Modify the text file from so that the counter only counts odd numbers: 001, 011, 101, 111, 001, etc.
library IEEE;
use IEEE.std_logic_1164.all;
entity mod4even is
port
(
clk : in std_logic;
reset : in std_logic;
Q : out std_logic_vector(2 downto 0)
);
end mod4even;
architecture behavioral of mod4even is
signal sig_Q : std_logic_vector(2 downto 0);
begin
process (clk)
begin
if (rising_edge(clk)) then
if reset =%u20191%u2019 then
sig_Q <= %u201D000%u201D;
else
case sig_Q is
when "000" => Sig_Q <= "010";
when "010" => Sig_Q <= "100";
when "100" => Sig_Q <= "110";
when "110" => Sig_Q <= "000";
when "001" => Sig_Q <= "000";
when "011" => Sig_Q <= "000";
when "101" => Sig_Q <= "000";
when "111" => Sig_Q <= "000";
when others => Sig_Q <= "000";
end case;
end if;
end if;
end process;
Q <= sig_Q;
end behavioral;
Explanation / Answer
library IEEE;
use IEEE.std_logic_1164.all;
entity mod4odd is
port
(
clk : in std_logic;
reset : in std_logic;
Q : out std_logic_vector(2 downto 0)
);
end mod4odd;
architecture behavioral of mod4odd is
signal sig_Q : std_logic_vector(2 downto 0);
begin
process (clk)
begin
if (rising_edge(clk)) then
if reset =%u20191%u2019 then
sig_Q <= %u201D001%u201D;
else
case sig_Q is
when "001" => Sig_Q <= "011";
when "011" => Sig_Q <= "101";
when "101" => Sig_Q <= "111";
when "111" => Sig_Q <= "001";
when "000" => Sig_Q <= "001";
when "010" => Sig_Q <= "001";
when "100" => Sig_Q <= "001";
when "110" => Sig_Q <= "001";
when others => Sig_Q <= "001";
end case;
end if;
end if;
end process;
Q <= sig_Q;
end behavioral;
/// i have shown the change as bold and italian case
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