library IEEE; use IEEE.STD_LOGIC_1164.all; entity Counter1 is port ( init, clk :
ID: 1839450 • Letter: L
Question
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Counter1 is port (
init, clk : in std_logic;
q0, q1, q2 : inout std_logic
);
end Counter1;
architecture dataflow of Counter1 is
begin
q0 <= '0' when init = '1' else
q1 when rising_edge (clk);
q1 <= '0' when init = '1' else
q2 when rising_edge (clk);
q2 <= '1' when init = '1' else
q0 when rising_edge (clk);
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sim is
end sim;
architecture behavior of sim is component Counter1 port (
init: in std_logic;
clk: in std_logic;
q0: out std_logic;
q1: out std_logic;
q2: out std_logic
);
end component;
signal init: std_logic := '0';
signal clk: std_logic := '0';
signal q0: std_logic;
signal q1: std_logic;
signal q2: std_logic;
begin
uut: Counter1 port map (
init => init,
clk => clk,
q0 => q0,
q1 => q1,
q2 => q2
);
process
begin
init <= '0'; clk <= '0'; wait for 500ns;
init <= '0'; clk <= '1'; wait for 500ns;
init <= '1'; clk <= '0'; wait for 500ns;
init <= '1'; clk <= '1'; wait;
end process;
END;
Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity syn_count3 is
port ( clk: in std_logic;
INIT: in std_logic;
q1,q2,q3 : inout std_logic );
end syn_count3;
--architecture of entity
architecture behavioural of syn_count3 is
signal q0, q1, q2, init, clk: STD_LOGIC :='0';
begin
q0 <= '0' when init = '1' else
q1 when rising_edge (clk);
q1 <= '0' when init = '1' else
q2 when rising_edge (clk);
q2 <= '1' when init = '1' else
q0 when rising_edge (clk);
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity testbench is
end testbench;
architecture behavioral of testbench is component
--signal declaration
signal init, clk: std_logic := '0';
signal q0,q1,q2: std_logic;
begin (process)
counter: syn_count3
port map (init, clk, q0, q1, q2);
process
begin
init <= '0'; clk <= '0'; wait for 500ns;
init <= '0'; clk <= '1'; wait for 500ns;
init <= '1'; clk <= '0'; wait for 500ns;
init <= '1'; clk <= '1'; wait;
end process;
END;
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