1. Use Verilog to design a module that performs one of four operations on two 4-
ID: 1835782 • Letter: 1
Question
1. Use Verilog to design a module that performs one of four operations on two 4-bit inputs to produce one 4-bit output as specified below. Usealways and casestatements, andbegin – end statements if needed. Include explanatory comments in the module’s Verilog code as needed. Use the text editor within ModelSim or any text editor that you like to write the Verilog code.
Inputs a[3;0], b[3:0], s[3:0]
Outputs y[3:0]
Function s function
0 y = a +b, unsigned add
1 y = a AND b, bit-wise AND
2 y = NOT a, bit-wise NOT of input a; ignore input b
3 y = 0, ignore inputs a and b
Explanation / Answer
module c1( input [3:0] a, input [3:0] b, input [3:0] s, output [3:0] y ); reg [3:0]temp; always begin if(s == 4'b0000) temp = a + b; else if(s == 4'b0001) temp = a&b; else if(s == 4'b0010) temp = !a; else temp = 0; end assign y = temp; endmodule
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