QuestionDetails: Consider a VLSI chip with 100,000 gates and 2000 flip flops. Ac

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QuestionDetails: Consider a VLSI chip with 100,000 gates and 2000 flip flops. Acombinational ATPG program produces 500 vectors to fully test thelogic. Find the minimum number of scan test cycles if 20 scanchains are implemented. Given that the circuit has 20 primary inputand 20 primary output data pins and only one extra pin availablefor test ,how much overhead will be needed for the new design? QuestionDetails: QuestionDetails: Consider a VLSI chip with 100,000 gates and 2000 flip flops. Acombinational ATPG program produces 500 vectors to fully test thelogic. Find the minimum number of scan test cycles if 20 scanchains are implemented. Given that the circuit has 20 primary inputand 20 primary output data pins and only one extra pin availablefor test ,how much overhead will be needed for the new design?

Explanation / Answer

Alright I will finish the problem for you Josh: Here are the equations i used to solve the question So total test cycles required = 1002500*20 +2k+4
Number of gates =100k (n2) Pin overhead =1 as 1 pin is given fortest. When only 1 pin is available, area overhead =[4n/(n2+10n) ] *100%             =8k/120k *100%             = 6.7 I hope this helps PLEASE RATE I hope this helps PLEASE RATE

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