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1. In the simulation run of the four-bit adder, when we performed the additions

ID: 1812346 • Letter: 1

Question

1. In the simulation run of the four-bit adder, when we performed the additions of 2 + 4 and 3 + 6 we did not immediately have an output of 6 and 9 respectively on SOUT. What could be the cause of this?

2. If we changed the count period to 100ns for AI and BI would this correct the anomalities in Question 1? why or why not?


3. How fast can your 4-bit adder/subtractor determine the sum or difference of two numbers?

4. Use the simulation timing diagram to compare the worse case time to do an operation with your ALU with the worst case using the 74LS381. State which operation takes the longest and list the time required for both ALU's.

Explanation / Answer

1 every gate have some delay typically in nanoseconds as adder has several gate level so there is some delay

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