The circuit below implements the basic RS latch. the RS Latch circuit can be vie

Question

The circuit below implements the basic RS latch. the RS Latch circuit can be viewed at: http://www.flickr.com/photos/79658186@N04/8214037462/in/photostream (a) Analyze the circuit and draw a detailed timing diagram. Assume that there is a delay of five time units for each gate and that Q output and the R and S are initially 0. Base your analysis on the following input sequence: (R,S) = (0,0),(01),(0,0),(1,0),and (0,0). (b) Repeat the analysis, using the min-typical or typical-max delay ranges from the vendor

Explanation / Answer

its complicated

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