A) How to decide the shortest possible clock period for a synchronous circuit wi

Question

A)
How to decide the shortest possible clock period for a synchronous
circuit with the flop-based clocking? What is the hold time of a register? How does the hold time
constrain the circuit delays for a synchronous circuit?

b) Consider a pipeline stage in a flop-based clocking scheme. The setup and
hold times for the flops are both 2 unit of time. The contamination and propagation delays of the
combinational logic are 3 and 5 units of time. The clock-to-q contamination and propagation
delays of the flops are both 1 unit of time. Can you clock the pipeline with a clock period of 7
units of time? Why?

C) Consider the flop-based clocking. How to fix setup and hold violations?
List all possible solutions by considering the following aspects:
1) Increase path delays; 2) decrease path delays; 3) work on fast paths; 4) work on slow
paths.

Explanation / Answer

Part b: We first need to understand what contamination and propagation delay are: -Contamination delay is the minimum time in which the output of a circuit will change when the inputs change. -Propagation delay is the maximum time required for the output of the circuit to change when the inputs change. Thus, using these definitions, we can write the following times as given in the problem for the circuit: Tsetup = 2 Thold = 2 Tcomb(min) = 3 (combinational contamination delay) Tcomb(max) = 5 (combinational propagation delay) Tcq(min) = Tcq(max) = 1 For any digital circuit, including pipelined circuits, the setup time constraint can be met if the circuit obeys the following equation: Tclk(min) >= Tcq(max) + Tcomb(max) + Tsetup Where Tclk(min) is the minimum clock period. In this case the period we are using is 7, so plug in our numbers and see if it works: 7 >= 1 + 5 + 2 = 8 7 is not >= 8, so the setup time would be violated in this circuit with a clock period of 7. We can't run it at that speed.

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