Do those a) FSM, sabotaged FSM, and testbench. All Verilog code must include emb

Question

Do those

a)       FSM, sabotaged FSM, and testbench. All Verilog code must include embedded explanatory comments,

b)       Simulation results proving that your module functions correctly: a log text file produced by $display statements in your testbench.

c)       A written statement explaining how your simulation results prove that both your module and testbench function correctly

Problem:

                          Figure 1: Vending Machine Block Diagram

The FSM has four input signals and one output signal. Their functions are specified in the table below. FSM inputs nickel and dime are assumed to be mutually exclusive; that is, only one of them can be ‘1’ at the same time.

Table 1: Vending Machine FSM inputs/outputs

Name

Direction

Function

clock

input

All signals in the vending machine are synchronized to the rising edge of this clock signal

reset

input

Resets the state machine to its initial state (S1)

nickel

input

High for one clock cycle indicates that a nickel has been deposited

dime

input

High for one clock cycle indicates that a dime has been deposited

dispense

output

High for one clock cycle dispenses a piece of candy

This vending machine dispenses candy under the following conditions:

a)       The machine accepts nickels and dimes.

b)       It takes 15 cents for a piece of candy to be dispensed.

c)       If 20 cents is deposited, the machine will not return the change, but it will credit the buyer with 5 cents toward the next purchase.

Derive a FSM that controls the vending machine as specified above. Write the Verilog FSM module using any of the FSM coding styles.

2. Write a Verilog testbench that:

a)       Uses sequential execution of Verilog tasks toverify your module for the following input sequences:

i.       Nickel-Nickel-Nickel                                

ii.      Nickel-Dime                              

iii.     Dime-Nickel                            

iv.    Dime-Dime-Dime (two pieces of candy should be dispensed)

The testbench should include the following tasks:

i.        “deposit_nickel” sets FSM input “nickel” to ‘1’ for one clock cycle, then returns it to ‘0’ and waits one clock cycle.

ii.     “deposit_dime” sets FSM input “dime” to ‘1’ for one clock cycle, then returns it to ‘0’and waits one clock cycle.

iii.     “NNN” calls “deposit_nickel” three times.

iv.     “ND” calls “deposit_nickel”, then “deposit_dime”.

v.       “DN”calls “deposit_dime”, then “deposit_nickel”.

vi.    “DDD” calls “deposit_dime” three times

b)       Checks that the module’s output is correct for all applied input sequences, and uses $display to print a pass/fail message to the console for each applied sequence.

3.    Check your testbench checker by sabotaging your FSM: introduce an error that causes one, and only one, incorrect state transition, and verify that your checker catches the erroneous transition and prints a “fail” message. Explain the nature of the sabotage in comments embedded within the sabotaged module Verilog code.

Name

Direction

Function

clock

input

All signals in the vending machine are synchronized to the rising edge of this clock signal

reset

input

Resets the state machine to its initial state (S1)

nickel

input

High for one clock cycle indicates that a nickel has been deposited

dime

input

High for one clock cycle indicates that a dime has been deposited

dispense

output

High for one clock cycle dispenses a piece of candy

Do those a) FSM, sabotaged FSM, and testbench. All Verilog code must include embedded explanatory comments, b) Simulation results proving that your module functions correctly: a log text file produced by $display statements in your testbench. c) A written statement explaining how your simulation results prove that both your module and testbench function correctly Problem: Use Verilog to design a finite state machine module that controls a coin-operated vending machine. The block diagram below shows the FSM in relation to other blocks within the vending machine system. You are designing the FSM only, not the coin sensor or candy release mechanism. Figure 1: Vending Machine Block Diagram The FSM has four input signals and one output signal. Their functions are specified in the table below. FSM inputs nickel and dime are assumed to be mutually exclusive; that is, only one of them can be ?1? at the same time. Table 1: Vending Machine FSM inputs/outputs Name Direction Function clock input All signals in the vending machine are synchronized to the rising edge of this clock signal reset input Resets the state machine to its initial state (S1) nickel input High for one clock cycle indicates that a nickel has been deposited dime input High for one clock cycle indicates that a dime has been deposited dispense output High for one clock cycle dispenses a piece of candy This vending machine dispenses candy under the following conditions: a) The machine accepts nickels and dimes. b) It takes 15 cents for a piece of candy to be dispensed. c) If 20 cents is deposited, the machine will not return the change, but it will credit the buyer with 5 cents toward the next purchase. Derive a FSM that controls the vending machine as specified above. Write the Verilog FSM module using any of the FSM coding styles. 2. Write a Verilog testbench that: a) Uses sequential execution of Verilog tasks toverify your module for the following input sequences: i. Nickel-Nickel-Nickel ii. Nickel-Dime iii. Dime-Nickel iv. Dime-Dime-Dime (two pieces of candy should be dispensed) The testbench should include the following tasks: i. deposit_nickel sets FSM input nickel to ?1? for one clock cycle, then returns it to ?0? and waits one clock cycle. ii. deposit_dime sets FSM input dime to ?1? for one clock cycle, then returns it to ?0?and waits one clock cycle. iii. NNN calls deposit_nickel three times. iv. ND calls deposit_nickel, then deposit_dime. v. DNcalls deposit_dime, then deposit_nickel. vi. DDD calls deposit_dime three times b) Checks that the module?s output is correct for all applied input sequences, and uses $display to print a pass/fail message to the console for each applied sequence. 3. Check your testbench checker by sabotaging your FSM: introduce an error that causes one, and only one, incorrect state transition, and verify that your checker catches the erroneous transition and prints a fail message. Explain the nature of the sabotage in comments embedded within the sabotaged module Verilog code.

Explanation / Answer

If you post but one question at a time, I'm sure more people would jump to help...

Related Questions

Navigate

• Browse (All)
• Browse D
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.