*Use Verilog HDL for coding* 1. (11 marks) Write a module for a 8 bit prefix add
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Question
*Use Verilog HDL for coding*
1. (11 marks) Write a module for a 8 bit prefix adder. Instantiate the module on DE2 board and design an appropriate test circuit. Then extend the design to produce a 2" bit prefix adder where n is an arbitrary integer- valued parameter. Test your design in a simulator, e.g. ModelSim, using an appropriate test-scheme. Marking Criteria: The mark is calculated according to the formula fa f t. The value of fa depends on the extent to which your circuit is able to meet the specifications of the 8 bit adder. If it satisfies all the requirements, then 3. If it meets a subset of the specifications then faExplanation / Answer
code :
#include <iostream>
#include <cmath>
Using name space std;
Int main() {
Float a, b, c, x1, x2, discriminant, realpart, imaginarypart;
Cout << “enter coefficients a, b and c: “;
discriminant =b*b -4*a*c;
If (discriminant > 0) {
X1 = (-b + sqrt(discriminant)) / (2*a);
X2 = (-b – sqrt(discriminant)) / (2*a);
cout << “Roots are real and different. “ << end1;
cout<< “x1 = “ << x1 << end1;
cout<< “x2 = “ << x2 << end1;
}
else if (discriminant == 0) {
cout << “Roots are real and samet. “ << end1;
X1 = (-b + sqrt(discriminant) / (2*a);
cout << “x1 = x2 =” << x1 << end1;
}
else {
realpart = -b/(2*a);
imaginarypart = sqrt(discriminant) / (2*a);
cout << “Roots are real and different. “ << end1;
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