Model a full-subtractor in VHDL at the structural gate level. The specifications

Question

Model a full-subtractor in VHDL at the structural gate level. The specifications for the ful subtractor model are given below: You are allowed to use only the following logic gates in your full-subtractor design: NOT, 2-input AND, 3-input OR and 3-input XOR The propagation delay for each NOT gate is 1 ns The propagation delay for each OR gate is 2 ns .The propagation delay for each AND gate is 2 ns The propagation delay for each XOR gate is 3ns Compile and load your VHDL full-subtractor program using ModelSim/Questa Sim .Using ModelSim, simulate the full-subtractor design for the following cases: 000, 001, 010, 011, 100, 101, 110, 111, XHL, HHL, L-L, ZOX Use the ModelSim/Questa Sim force command in order to assign values to the input signals of your design

Explanation / Answer

Full substractor using structural modelling

-- VHDL CODE FOR NOT GATE

library ieee;
use ieee.std_logic_1164.all;

entity not1_gate is
port(x:in bit;y:out bit);
end not1_gate;

architecture not1 of not1_gate is
begin
y<=not x after 1ns;
end not1;

-----------------------------------------------------------
-- VHDL CODE FOR XOR GATE
library ieee;
use ieee.std_logic_1164.all;

entity xor2_gate is
port(a,b:in bit;y:out bit);
end kanhe_xor2;

architecture xor2 of xor2_gate is
begin
y<=a xor b after 3ns ;
end xor2;
--------------------------------------------------------------
-- VHDL CODE FOR OR GATE

library ieee;
use ieee.std_logic_1164.all;

entity or2_gate is
port(a,b:in bit;y:out bit);
end or2_gate;

architecture or2 of or2_gate is
begin
y<=a or b after 2ns;
end or2;
------------------------------------------------------------------
-- VHDL CODE FOR AND GATE

Library ieee;
use ieee.std_logic_1164.all;

entity and2_gate is
port(a,b:in bit;y:out bit);
end and2_gate;

architecture and2 of and2_gate is
begin
y <= a and b after 2ns;
end and2;

--------------------------------------------------------------------

-- MAIN PROGRAM
--------------------------------------------------------------------------------------------------------
------------- DIFFERENCE = A_IN XOR B_IN XOR C_IN
------------- BORROW = ((NOT A) AND B) OR ( NOT(A_IN XOR B_IN) AND C_IN)
---------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(A_IN,B_IN,C_IN:in bit;D_OUT,B_OUT:out bit);
end full_sub;

architecture struct of full_sub is

--COMPONENT INSTANTIATION
component and2_gate is
port(a,b:in bit;y:out bit);
end component;

component xor2_gate is
port(a,b:in bit;y:out bit);
end component;

component or_gate is
port(a,b:in bit;y:out bit);
end component;

component not1_gate is
port(x:in bit;y:out bit);
end component;

signal S0,S1,S2,S3,S4,S5:bit;

begin

X1: xor2_gate port map(A_IN,B_IN,S0);
X2: xor2_gate port map(S0,C_IN,D_OUT);

N1: not1_gate port map(A_IN,S1);
A1: and2_gate port map(S1,B_IN,S2);

N2: not1_gate port map(S0, S3);
A2: and2_gate port map(S3,C_IN,S4);

O1: or2_gate port map(S2,S4,B_OUT);

end struct;

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