Sunset April 30 at 5:00 pm Homework 5 You are to implement the following in VHDL
ID: 1766007 • Letter: S
Question
Sunset April 30 at 5:00 pm Homework 5 You are to implement the following in VHDL: 1. D flip-flop 2. D flip-flop 3. J-K flip flop with asynchronous set 4. T Flip flop with asynchronous clear with enable and reset Write the corresponding VHDL code. Also, write thorough. Use ModelSim to thoroughly simulate the above are testing. Video should be 4 to 5 minutes lon Turn in: Your VHDL code should be in text format, NOT at all. Testbench code: Your testbench code should b equal to not turning it in at all. thorough simulationsExplanation / Answer
VHLD code of D flip flop-
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity D_FF is
PORT( D,CLOCK: in std_logic;
Q: out std_logic);
end D_FF;
architecture behavioral of D_FF is
begin
process(CLOCK)
begin
if(CLOCK='1' and CLOCK'EVENT) then
Q <= D;
end if;
end process;
end behavioral;
VHDL code for D flip flop with enable and reset-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clk).
--Note that the reset input has the highest priority,Set being the next highest
--priority and clock enable having the lowest priority.
entity example_FDRSE is
port(
Q : out std_logic; -- Data output
CLK :in std_logic; -- Clock input
CE :in std_logic; -- Clock enable input
RESET :in std_logic; -- Synchronous reset input
D :in std_logic; -- Data input
SET : in std_logic -- Synchronous set input
);
end example_FDRSE;
architecture Behavioral of example_FDRSE is --architecture of the circuit.
begin --"begin" statement for architecture.
process(CLK) --process with sensitivity list.
begin --"begin" statment for the process.
if ( rising_edge(CLK) ) then --This makes the process synchronous(with clock)
if (RESET = '1') then
Q <= '0';
else
if(SET = '1') then
Q <= '1';
else
if ( CE = '1') then
Q <= D;
end if;
end if;
end if;
end if;
end process; --end of process statement.
end Behavioral;
VHDL code for J-K flip flop with asynchrounous set-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JKFF1 is
Port ( j,k,clk,reset : in STD_LOGIC;
Q : inout STD_LOGIC);
end JKFF1;
architecture Behavioral of JKFF1 is
signal div:std_logic_vector(22 downto 0);
signal clkd:std_logic;
begin
process(clk)
begin
if rising_edge(clk)then
div<= div+1;
end if;
end process;
clkd<=div(22);
process(clkd,reset)
begin
if(reset='1')then
Q<= '0';
elsif(clkd'event and clkd='1')then
if(j='0' and k='0')then
Q<= Q;
elsif(j='0' and k='1')then
Q<= '0';
elsif(j='1' and k='0')then
Q<= '1';
elsif(j='1' and k='1')then
Q<= not Q;
end if;
end if;
end process;
end Behavioral;
VHDL code for T flip flop with asynchrounous clear-
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