280256 28C256 28C256 28C256 WE A1 A1 A1 A1 A1 A2 B A2 8 A2 B A3 A3 11 0O 12 0 13
ID: 1765988 • Letter: 2
Question
280256 28C256 28C256 28C256 WE A1 A1 A1 A1 A1 A2 B A2 8 A2 B A3 A3 11 0O 12 0 13 02 15 00 16 04 17 05 11 DO 11 DO O0 12 D1 12 01 01 01 A5 5 13 D2 15 03 A7 16 04 04 04 AS 24 A9 18 D6 A10 A11 A12 A13 A14 19 07 19 07 1907 A11 23 A11 A12 A13 A14 A11 A11 A12 A12A12 A13 26 A13 A13 A13 A13 A14 A14 OE A16 A17 A18 A19 DO D1 D2 D3 D4 DS D6 OE U3 U4 A18 19-0] D17-0 A19 1 74x10 2 74x139 2 HIMEM L IG 1YO SEB000 L U6 A 1Y2 A16 SFB000 READ WRITE WRL Figure 9-12 Address decoding and EEPROM enabling in a microprocessor system. From Digital Design: Principles and Practices, Fourth Edition. John F. Wakerly, ISBN 0-13-186389-4 2006, Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.Explanation / Answer
Memory
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
EEPROM1
Start Address
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xE0000
EEPROM1
End Address
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xE7FFF
EEPROM2
Start Address
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xE8000
EEPROM2
End Address
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xEFFFF
EEPROM3
Start Address
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF0000
EEPROM3
End Address
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xF7FFF
EEPROM4
Start Address
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF8000
EEPROM4
End Address
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xFFFFF
Here A19 = A18 = A17 = 1 at the input of NAND gate generates an active LOW signal as strobe to 74139 decoder.
A16A15 = 00 for enabling Chip Select for EEPROM 1
A16A15 = 01 for enabling Chip Select for EEPROM 2
A16A15 = 10 for enabling Chip Select for EEPROM 3
A16A15 = 11 for enabling Chip Select for EEPROM 4
Memory
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
EEPROM1
Start Address
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xE0000
EEPROM1
End Address
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xE7FFF
EEPROM2
Start Address
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xE8000
EEPROM2
End Address
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xEFFFF
EEPROM3
Start Address
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF0000
EEPROM3
End Address
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xF7FFF
EEPROM4
Start Address
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF8000
EEPROM4
End Address
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xFFFFF
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