4.3 (9 points) Refer to Figure L4. The block diagram of the parity detector FSM

Question

4.3 (9 points) Refer to Figure L4. The block diagram of the parity detector FSM similar to lab 10 is shown. The system accepts an input signal and outputs the signal's parity. The system also accepts a Reset signal that is polled fast enough to behave asynchronously. Based on the functionality of the code in the block diagram, determine which DIO line is used for polling the Reset signal. When the reset signal is true, determine the next state of the system and the parity detector output. Reset: Next State: Output

Explanation / Answer

The system accepts the input signal as either high or low logic (i.e. 1 or 0).

we have obtain the output only when we provide high logic (i.e. 1) in the input

The reset signal is always high logic (i.e. 1)

Next State is also high logic (i.e. 1)

Then the output of the parity detector is odd parity

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