Using Structural Modeling in VHDL write the code for: An Arithmetic Logic Unit (
ID: 1730376 • Letter: U
Question
Using Structural Modeling in VHDL write the code for:
An Arithmetic Logic Unit (ALU) shown in the figure below. A (16-bit), B (16-bit), Opcode (3-bit), and Mode (1-bit) are the inputs; and ALUOut (16-bit) and Cout (1-bit) are the outputs of the design. A and B hold the values of the operands. Mode and Opcode together indicate the type of the operation performed by ALU.
The ALU components ARE:
-Arithmetic Unit that consists of one 16-bit adder, 16-bit subtractor, 16-bit incrementer, and 8-bit multiplier
-16-bit Logic Unit which performs the following operations: A and B, A or B, A nand B, A nor B, A xor B, A xnor B, Not A and Not B
-16-bit Shifter unit with A, B, Type and Direction as inputs and ShiftOut as output. The value of A should be shifted by the value specified in B. The “Direction” bit is used to determine whether to shift left (0) or right (1) and the “Type” bit is used to determine whether to Shift (0) or Rotate (1) the data
-16-bit 2-to-1 Multiplexer. The MUXes are utilized in order to route the outputs of functional units to ALU output
-Controller that is responsible for generating the required control signals for all functional blocks in your design. Select is used to select the functional unit for the corresponding operation in Arithmetic Unit. Sel1 and Sel2 are utilized as select signals of MUXes. Sel_Cout is used to control the cout of ALU, its value is “1” when ALU doing arithmetical operations; otherwise, it is “0”. Direction bit determines the direction of shift operation and Type bit determines the way of shifting. Opcode is used to select the type of operation and could be used as input to all three functional units.
Please Provide WAVEFORMS
T he following table summarizes the overall behavior of the ALU: Mode 0 0 0 0 0 0 0 0 Operation A nor B A nand E A or B A and B A xor B A xnor B Not A Not B Opcode 001 010 011 100 101 110 001 010 011 100 101 110 Increment A (A +1) Shift Left(A,B) Shift Right(A,B) Rotate Left(A,B) Rotate Right(A,B)Explanation / Answer
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
-----------------------------------------------
---------- ALU 8-bit VHDL ---------------------
-----------------------------------------------
entity ALU is
generic (
constant N: natural := 1 -- number of shifted or rotated bits
);
Port (
A, B : in STD_LOGIC_VECTOR(15 downto 0); -- 2 inputs 16-bit
ALU_Sel : in STD_LOGIC_VECTOR(2 downto 0); -- 1 input 3-bit for selecting function
ALU_SEL1 : in STD_LOGIC
X : out STD_LOGIC_VECTOR (15 downto 0));
ALU_type: in STD_LOGIC
ALU_Dir: in STD_LOGIC
ALU_Mode :in STD_LOGIC_VECTOR(1);
ALU_Type : in STD_LOGIC_VECTOR(
ALU_Out : out STD_LOGIC_VECTOR(15 downto 0); -- 1 output 16-bit
Cout : out std_logic -- Cout flag
);
end ALU;
architecture Behavioral of ALU is
signal ALU_Result : std_logic_vector (15 downto 0);
signal tmp: std_logic_vector (15 downto 0);
X <= A when (ALU_SEL1 = '1') else B; --mux
if ALU_Mode=1 then
begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "001" => -- Multiplication
ALU_Result <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) * to_integer(unsigned(B))),8)) ;
when "001" => -- Addition
ALU_Result <= A + B ;
when "010" => -- Subtraction
ALU_Result <= A - B ;
when "011" => -- INCREMENT
ALU_Result <= A + 1;
when "100" => -- Logical shift left
ALU_Result <= std_logic_vector(unsigned(A) sll N);
when "101" => -- Logical shift right
ALU_Result <= std_logic_vector(unsigned(A) srl N);
when "110" => -- Rotate left
ALU_Result <= std_logic_vector(unsigned(A) rol N);
when "111" => -- Rotate right
ALU_Result <= std_logic_vector(unsigned(A) ror N);
else
begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "000" => -- Logical and
ALU_Result <= A nor B;
when "001" => -- Logical or
ALU_Result <= A nand B;
when "010" => -- Logical xor
ALU_Result <= A or B;
when "011" => -- Logical nor
ALU_Result <= A and B;
when "100" => -- Logical nand
ALU_Result <= A xor B;
when "101" => -- Logical xnor
ALU_Result <= A xnor B;
when "110" => -- Not A
ALU_Result <= NOT A;
when "111" => -- Not B
ALU_Result <= NOT B;
when others => ALU_Result <= A + B ;
end case;
end if;
end process;
ALU_Out <= ALU_Result; -- ALU out
if mode=0 then
Cout=0;
else
Cout=1;
end if;
if Dir=0 then
-- Left Shift
r_Unsigned_L <= shift_left(unsigned(r_Shift1), 1);
r_Signed_L <= shift_left(signed(r_Shift1), 1);
else
-- Right Shift
r_Unsigned_R <= shift_right(unsigned(r_Shift1), 2);
r_Signed_R <= shift_right(signed(r_Shift1), 2);
end if;
end architecture behave;
Testbench VHDL code for ALU:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
ENTITY tb_ALU IS
END tb_ALU;
ARCHITECTURE behavior OF tb_ALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
A, B : in STD_LOGIC_VECTOR(15 downto 0); -- 2 inputs 16-bit
ALU_Sel : in STD_LOGIC_VECTOR(2 downto 0); -- 1 input 3-bit for selecting function
ALU_SEL1 : in STD_LOGIC
ALU_X : out STD_LOGIC_VECTOR (15 downto 0));
ALU_type: in STD_LOGIC
ALU_Dir: in STD_LOGIC
ALU_Mode :in STD_LOGIC_VECTOR(1);
ALU_Type : in STD_LOGIC_VECTOR(
ALU_Out : out STD_LOGIC_VECTOR(15 downto 0); -- 1 output 16-bit
Cout : out std_logic -- Cout flag
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal ALU_Sel : std_logic_vector(2 downto 0) := (others => '0');
signal ALU_Sel1 : std_logic_vector := (others => '0');
signal ALU_Type:std_logic_vector:= others => '0');
signal ALU_Mode:std_logic_vector := others => '0');
signal ALU_dir:std_logic_vector(1)L others => '0');
--Outputs
signal ALU_Out : std_logic_vector(15 downto 0);
signal Cout : std_logic;
signal i:integer;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
A => A,
B => B,
ALU_Sel => ALU_Sel,
ALU_Out => ALU_Out,
Cout => Cout,
ALU_Sel1 => ALU_Sel1,
ALU_type=ALU_type;
ALU_dir=ALU_dir;
ALU_Mode=ALU_Mode;
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A <= x"0AAA";
B <= x"0235";
ALU_Sel <= x"0”;
ALU_Sel1 <=1;
ALU_dir<=1;
ALU_Mode<=1;
for i in 0 to 15 loop
ALU_Sel <= ALU_Sel + x"1";
wait for 100 ns;
end loop;
A <= x"05CA";
B <= x"0143";
ALU_Sel <= x"3”;
ALU_Sel1 <=0;
ALU_dir<=0;
ALU_Mode<=0;
wait;
end process;
END;
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